pwm.fit.summary

实现PWM波型....使用VHDL语言

Flow Status : Successful - Mon May 14 22:16:56 2007
Quartus II Version : 5.0 Build 171 11/03/2005 SP 2 SJ Full Version
Revision Name : pwm
Top-level Entity Name : pwm
Family : Stratix
Met timing requirements : N/A
Total logic elements : 30 / 10,570 ( < 1 % )
Total pins : 11 / 336 ( 3 % )
Total virtual pins : 0
Total memory bits : 0 / 920,448 ( 0 % )
DSP block 9-bit elements : 0 / 48 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )
Device : EP1S10F484C5
Timing Models : Final