pwm.fit.qmsg

实现PWM波型....使用VHDL语言

{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_MAC_RAM_PACKING" "" "Info: Finished moving registers into LUTs, I/O cells, DSP blocks, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "10 unused 3.30 9 1 0 " "Info: Number of I/O pins in group: 10 (unused VREF, 3.30 VCCIO, 9 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 0 39 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  39 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 39 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  39 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 43 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  43 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 1 44 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  44 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use unused 1 38 " "Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  38 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use unused 0 39 " "Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  39 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use unused 0 45 " "Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  45 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use unused 0 44 " "Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  44 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "9 does not use unused 0 6 " "Info: I/O bank number 9 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "10 does not use unused 0 0 " "Info: I/O bank number 10 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "11 does not use unused 0 6 " "Info: I/O bank number 11 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "12 does not use unused 0 0 " "Info: I/O bank number 12 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.084 ns register register " "Info: Estimated most critical path is register to register delay of 3.084 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fenpincount\[0\] 1 REG LAB_X36_Y14 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X36_Y14; Fanout = 4; REG Node = 'fenpincount\[0\]'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "" { fenpincount[0] } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.120 ns) + CELL(0.459 ns) 0.579 ns reduce_nor~47 2 COMB LAB_X36_Y14 1 " "Info: 2: + IC(0.120 ns) + CELL(0.459 ns) = 0.579 ns; Loc. = LAB_X36_Y14; Fanout = 1; COMB Node = 'reduce_nor~47'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "0.579 ns" { fenpincount[0] reduce_nor~47 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.493 ns) + CELL(0.213 ns) 1.285 ns reduce_nor~0 3 COMB LAB_X35_Y14 5 " "Info: 3: + IC(0.493 ns) + CELL(0.213 ns) = 1.285 ns; Loc. = LAB_X35_Y14; Fanout = 5; COMB Node = 'reduce_nor~0'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "0.706 ns" { reduce_nor~47 reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.428 ns) + CELL(0.344 ns) 2.057 ns mycounter\[0\]~118 4 COMB LAB_X35_Y14 2 " "Info: 4: + IC(0.428 ns) + CELL(0.344 ns) = 2.057 ns; Loc. = LAB_X35_Y14; Fanout = 2; COMB Node = 'mycounter\[0\]~118'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "0.772 ns" { reduce_nor~0 mycounter[0]~118 } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 2.117 ns mycounter\[1\]~114 5 COMB LAB_X35_Y14 2 " "Info: 5: + IC(0.000 ns) + CELL(0.060 ns) = 2.117 ns; Loc. = LAB_X35_Y14; Fanout = 2; COMB Node = 'mycounter\[1\]~114'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "0.060 ns" { mycounter[0]~118 mycounter[1]~114 } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 2.177 ns mycounter\[2\]~110 6 COMB LAB_X35_Y14 2 " "Info: 6: + IC(0.000 ns) + CELL(0.060 ns) = 2.177 ns; Loc. = LAB_X35_Y14; Fanout = 2; COMB Node = 'mycounter\[2\]~110'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "0.060 ns" { mycounter[1]~114 mycounter[2]~110 } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 2.237 ns mycounter\[3\]~106 7 COMB LAB_X35_Y14 2 " "Info: 7: + IC(0.000 ns) + CELL(0.060 ns) = 2.237 ns; Loc. = LAB_X35_Y14; Fanout = 2; COMB Node = 'mycounter\[3\]~106'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "0.060 ns" { mycounter[2]~110 mycounter[3]~106 } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.219 ns) 2.456 ns mycounter\[4\]~102 8 COMB LAB_X35_Y14 3 " "Info: 8: + IC(0.000 ns) + CELL(0.219 ns) = 2.456 ns; Loc. = LAB_X35_Y14; Fanout = 3; COMB Node = 'mycounter\[4\]~102'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "0.219 ns" { mycounter[3]~106 mycounter[4]~102 } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.628 ns) 3.084 ns mycounter\[7\] 9 REG LAB_X35_Y14 2 " "Info: 9: + IC(0.000 ns) + CELL(0.628 ns) = 3.084 ns; Loc. = LAB_X35_Y14; Fanout = 2; REG Node = 'mycounter\[7\]'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "0.628 ns" { mycounter[4]~102 mycounter[7] } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.043 ns 66.25 % " "Info: Total cell delay = 2.043 ns ( 66.25 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.041 ns 33.75 % " "Info: Total interconnect delay = 1.041 ns ( 33.75 % )" {  } {  } 0}  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "3.084 ns" { fenpincount[0] reduce_nor~47 reduce_nor~0 mycounter[0]~118 mycounter[1]~114 mycounter[2]~110 mycounter[3]~106 mycounter[4]~102 mycounter[7] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue May 15 10:26:58 2007 " "Info: Processing ended: Tue May 15 10:26:58 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0}  } {  } 0}