pwm.fit.qmsg

实现PWM波型....使用VHDL语言

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 15 10:26:48 2007 " "Info: Processing started: Tue May 15 10:26:48 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=on --write_settings_files=off pwm -c pwm " "Info: Command: quartus_fit --read_settings_files=on --write_settings_files=off pwm -c pwm" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "pwm EP1S10B672C6 " "Info: Selected device EP1S10B672C6 for design \"pwm\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S20B672C6 " "Info: Device EP1S20B672C6 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S25B672C6 " "Info: Device EP1S25B672C6 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "11 11 " "Info: No exact pin location assignment(s) for 11 pins of 11 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "pwmout " "Info: Pin pwmout not assigned to an exact location on the device" {  } { { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.vhd" 9 -1 0 } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "pwmout" } } } } { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "" { pwmout } "NODE_NAME" } "" } } { "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.fld" "" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.fld" "" "" { pwmout } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "countclk " "Info: Pin countclk not assigned to an exact location on the device" {  } { { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.vhd" 6 -1 0 } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "countclk" } } } } { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "" { countclk } "NODE_NAME" } "" } } { "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.fld" "" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.fld" "" "" { countclk } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "rs " "Info: Pin rs not assigned to an exact location on the device" {  } { { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.vhd" 7 -1 0 } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rs" } } } } { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "" { rs } "NODE_NAME" } "" } } { "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.fld" "" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.fld" "" "" { rs } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "dat\[7\] " "Info: Pin dat\[7\] not assigned to an exact location on the device" {  } { { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.vhd" 8 -1 0 } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dat\[7\]" } } } } { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "" { dat[7] } "NODE_NAME" } "" } } { "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.fld" "" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.fld" "" "" { dat[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "dat\[6\] " "Info: Pin dat\[6\] not assigned to an exact location on the device" {  } { { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.vhd" 8 -1 0 } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dat\[6\]" } } } } { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "" { dat[6] } "NODE_NAME" } "" } } { "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.fld" "" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.fld" "" "" { dat[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "dat\[5\] " "Info: Pin dat\[5\] not assigned to an exact location on the device" {  } { { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.vhd" 8 -1 0 } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dat\[5\]" } } } } { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "" { dat[5] } "NODE_NAME" } "" } } { "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.fld" "" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.fld" "" "" { dat[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "dat\[4\] " "Info: Pin dat\[4\] not assigned to an exact location on the device" {  } { { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.vhd" 8 -1 0 } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dat\[4\]" } } } } { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "" { dat[4] } "NODE_NAME" } "" } } { "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.fld" "" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.fld" "" "" { dat[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "dat\[3\] " "Info: Pin dat\[3\] not assigned to an exact location on the device" {  } { { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.vhd" 8 -1 0 } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dat\[3\]" } } } } { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "" { dat[3] } "NODE_NAME" } "" } } { "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.fld" "" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.fld" "" "" { dat[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "dat\[2\] " "Info: Pin dat\[2\] not assigned to an exact location on the device" {  } { { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.vhd" 8 -1 0 } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dat\[2\]" } } } } { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "" { dat[2] } "NODE_NAME" } "" } } { "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.fld" "" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.fld" "" "" { dat[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "dat\[1\] " "Info: Pin dat\[1\] not assigned to an exact location on the device" {  } { { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.vhd" 8 -1 0 } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dat\[1\]" } } } } { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "" { dat[1] } "NODE_NAME" } "" } } { "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.fld" "" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.fld" "" "" { dat[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "dat\[0\] " "Info: Pin dat\[0\] not assigned to an exact location on the device" {  } { { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.vhd" 8 -1 0 } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dat\[0\]" } } } } { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "" { dat[0] } "NODE_NAME" } "" } } { "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.fld" "" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.fld" "" "" { dat[0] } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "countclk Global clock in PIN M24 " "Info: Automatically promoted signal \"countclk\" to use Global clock in PIN M24" {  } { { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.vhd" 6 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Start inferring scan chains for DSP blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Inferring scan chains for DSP blocks is complete" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_MAC_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density" {  } {  } 0}