pwm.tan.qmsg

实现PWM波型....使用VHDL语言

{ "Info" "ITDB_FULL_TCO_RESULT" "countclk pwmout theout 7.496 ns register " "Info: tco from clock \"countclk\" to destination pin \"pwmout\" through register \"theout\" is 7.496 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "countclk source 3.102 ns + Longest register " "Info: + Longest clock path from clock \"countclk\" to source register is 3.102 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns countclk 1 CLK PIN_M24 17 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_M24; Fanout = 17; CLK Node = 'countclk'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "" { countclk } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.782 ns) + CELL(0.560 ns) 3.102 ns theout 2 REG LC_X34_Y14_N9 1 " "Info: 2: + IC(1.782 ns) + CELL(0.560 ns) = 3.102 ns; Loc. = LC_X34_Y14_N9; Fanout = 1; REG Node = 'theout'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "2.342 ns" { countclk theout } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.320 ns 42.55 % " "Info: Total cell delay = 1.320 ns ( 42.55 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.782 ns 57.45 % " "Info: Total interconnect delay = 1.782 ns ( 57.45 % )" {  } {  } 0}  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "3.102 ns" { countclk theout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "3.102 ns" { countclk countclk~out0 theout } { 0.000ns 0.000ns 1.782ns } { 0.000ns 0.760ns 0.560ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" {  } {  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.218 ns + Longest register pin " "Info: + Longest register to pin delay is 4.218 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns theout 1 REG LC_X34_Y14_N9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y14_N9; Fanout = 1; REG Node = 'theout'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "" { theout } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.714 ns) + CELL(2.504 ns) 4.218 ns pwmout 2 PIN PIN_AF17 0 " "Info: 2: + IC(1.714 ns) + CELL(2.504 ns) = 4.218 ns; Loc. = PIN_AF17; Fanout = 0; PIN Node = 'pwmout'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "4.218 ns" { theout pwmout } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.504 ns 59.36 % " "Info: Total cell delay = 2.504 ns ( 59.36 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.714 ns 40.64 % " "Info: Total interconnect delay = 1.714 ns ( 40.64 % )" {  } {  } 0}  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "4.218 ns" { theout pwmout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "4.218 ns" { theout pwmout } { 0.000ns 1.714ns } { 0.000ns 2.504ns } } }  } 0}  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "3.102 ns" { countclk theout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "3.102 ns" { countclk countclk~out0 theout } { 0.000ns 0.000ns 1.782ns } { 0.000ns 0.760ns 0.560ns } } } { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "4.218 ns" { theout pwmout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "4.218 ns" { theout pwmout } { 0.000ns 1.714ns } { 0.000ns 2.504ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "theout dat\[7\] countclk -3.131 ns register " "Info: th for register \"theout\" (data pin = \"dat\[7\]\", clock pin = \"countclk\") is -3.131 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "countclk destination 3.102 ns + Longest register " "Info: + Longest clock path from clock \"countclk\" to destination register is 3.102 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns countclk 1 CLK PIN_M24 17 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_M24; Fanout = 17; CLK Node = 'countclk'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "" { countclk } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.782 ns) + CELL(0.560 ns) 3.102 ns theout 2 REG LC_X34_Y14_N9 1 " "Info: 2: + IC(1.782 ns) + CELL(0.560 ns) = 3.102 ns; Loc. = LC_X34_Y14_N9; Fanout = 1; REG Node = 'theout'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "2.342 ns" { countclk theout } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.320 ns 42.55 % " "Info: Total cell delay = 1.320 ns ( 42.55 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.782 ns 57.45 % " "Info: Total interconnect delay = 1.782 ns ( 57.45 % )" {  } {  } 0}  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "3.102 ns" { countclk theout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "3.102 ns" { countclk countclk~out0 theout } { 0.000ns 0.000ns 1.782ns } { 0.000ns 0.760ns 0.560ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } {  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.333 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.333 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.141 ns) 1.141 ns dat\[7\] 1 PIN PIN_AA17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_AA17; Fanout = 1; PIN Node = 'dat\[7\]'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "" { dat[7] } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.382 ns) + CELL(0.087 ns) 5.610 ns LessThan~105 2 COMB LC_X34_Y14_N7 1 " "Info: 2: + IC(4.382 ns) + CELL(0.087 ns) = 5.610 ns; Loc. = LC_X34_Y14_N7; Fanout = 1; COMB Node = 'LessThan~105'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "4.469 ns" { dat[7] LessThan~105 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.359 ns) + CELL(0.364 ns) 6.333 ns theout 3 REG LC_X34_Y14_N9 1 " "Info: 3: + IC(0.359 ns) + CELL(0.364 ns) = 6.333 ns; Loc. = LC_X34_Y14_N9; Fanout = 1; REG Node = 'theout'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "0.723 ns" { LessThan~105 theout } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.592 ns 25.14 % " "Info: Total cell delay = 1.592 ns ( 25.14 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.741 ns 74.86 % " "Info: Total interconnect delay = 4.741 ns ( 74.86 % )" {  } {  } 0}  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "6.333 ns" { dat[7] LessThan~105 theout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "6.333 ns" { dat[7] dat[7]~out0 LessThan~105 theout } { 0.000ns 0.000ns 4.382ns 0.359ns } { 0.000ns 1.141ns 0.087ns 0.364ns } } }  } 0}  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "3.102 ns" { countclk theout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "3.102 ns" { countclk countclk~out0 theout } { 0.000ns 0.000ns 1.782ns } { 0.000ns 0.760ns 0.560ns } } } { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "6.333 ns" { dat[7] LessThan~105 theout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "6.333 ns" { dat[7] dat[7]~out0 LessThan~105 theout } { 0.000ns 0.000ns 4.382ns 0.359ns } { 0.000ns 1.141ns 0.087ns 0.364ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue May 15 10:27:21 2007 " "Info: Processing ended: Tue May 15 10:27:21 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}