pwm.tan.qmsg

实现PWM波型....使用VHDL语言

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "countclk " "Info: Assuming node \"countclk\" is an undefined clock" {  } { { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.vhd" 6 -1 0 } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "countclk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "countclk register fenpincount\[4\] register theout 249.07 MHz 4.015 ns Internal " "Info: Clock \"countclk\" has Internal fmax of 249.07 MHz between source register \"fenpincount\[4\]\" and destination register \"theout\" (period= 4.015 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.829 ns + Longest register register " "Info: + Longest register to register delay is 3.829 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fenpincount\[4\] 1 REG LC_X36_Y14_N4 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X36_Y14_N4; Fanout = 3; REG Node = 'fenpincount\[4\]'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "" { fenpincount[4] } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.594 ns) + CELL(0.459 ns) 1.053 ns reduce_nor~48 2 COMB LC_X35_Y14_N9 1 " "Info: 2: + IC(0.594 ns) + CELL(0.459 ns) = 1.053 ns; Loc. = LC_X35_Y14_N9; Fanout = 1; COMB Node = 'reduce_nor~48'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "1.053 ns" { fenpincount[4] reduce_nor~48 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.584 ns) + CELL(0.213 ns) 1.850 ns reduce_nor~0 3 COMB LC_X35_Y14_N8 5 " "Info: 3: + IC(0.584 ns) + CELL(0.213 ns) = 1.850 ns; Loc. = LC_X35_Y14_N8; Fanout = 5; COMB Node = 'reduce_nor~0'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "0.797 ns" { reduce_nor~48 reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.564 ns) + CELL(0.332 ns) 2.746 ns theout~0 4 COMB LC_X34_Y14_N8 1 " "Info: 4: + IC(0.564 ns) + CELL(0.332 ns) = 2.746 ns; Loc. = LC_X34_Y14_N8; Fanout = 1; COMB Node = 'theout~0'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "0.896 ns" { reduce_nor~0 theout~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.357 ns) + CELL(0.726 ns) 3.829 ns theout 5 REG LC_X34_Y14_N9 1 " "Info: 5: + IC(0.357 ns) + CELL(0.726 ns) = 3.829 ns; Loc. = LC_X34_Y14_N9; Fanout = 1; REG Node = 'theout'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "1.083 ns" { theout~0 theout } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.730 ns 45.18 % " "Info: Total cell delay = 1.730 ns ( 45.18 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.099 ns 54.82 % " "Info: Total interconnect delay = 2.099 ns ( 54.82 % )" {  } {  } 0}  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "3.829 ns" { fenpincount[4] reduce_nor~48 reduce_nor~0 theout~0 theout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "3.829 ns" { fenpincount[4] reduce_nor~48 reduce_nor~0 theout~0 theout } { 0.000ns 0.594ns 0.584ns 0.564ns 0.357ns } { 0.000ns 0.459ns 0.213ns 0.332ns 0.726ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "countclk destination 3.102 ns + Shortest register " "Info: + Shortest clock path from clock \"countclk\" to destination register is 3.102 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns countclk 1 CLK PIN_M24 17 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_M24; Fanout = 17; CLK Node = 'countclk'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "" { countclk } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.782 ns) + CELL(0.560 ns) 3.102 ns theout 2 REG LC_X34_Y14_N9 1 " "Info: 2: + IC(1.782 ns) + CELL(0.560 ns) = 3.102 ns; Loc. = LC_X34_Y14_N9; Fanout = 1; REG Node = 'theout'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "2.342 ns" { countclk theout } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.320 ns 42.55 % " "Info: Total cell delay = 1.320 ns ( 42.55 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.782 ns 57.45 % " "Info: Total interconnect delay = 1.782 ns ( 57.45 % )" {  } {  } 0}  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "3.102 ns" { countclk theout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "3.102 ns" { countclk countclk~out0 theout } { 0.000ns 0.000ns 1.782ns } { 0.000ns 0.760ns 0.560ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "countclk source 3.102 ns - Longest register " "Info: - Longest clock path from clock \"countclk\" to source register is 3.102 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns countclk 1 CLK PIN_M24 17 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_M24; Fanout = 17; CLK Node = 'countclk'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "" { countclk } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.782 ns) + CELL(0.560 ns) 3.102 ns fenpincount\[4\] 2 REG LC_X36_Y14_N4 3 " "Info: 2: + IC(1.782 ns) + CELL(0.560 ns) = 3.102 ns; Loc. = LC_X36_Y14_N4; Fanout = 3; REG Node = 'fenpincount\[4\]'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "2.342 ns" { countclk fenpincount[4] } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.320 ns 42.55 % " "Info: Total cell delay = 1.320 ns ( 42.55 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.782 ns 57.45 % " "Info: Total interconnect delay = 1.782 ns ( 57.45 % )" {  } {  } 0}  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "3.102 ns" { countclk fenpincount[4] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "3.102 ns" { countclk countclk~out0 fenpincount[4] } { 0.000ns 0.000ns 1.782ns } { 0.000ns 0.760ns 0.560ns } } }  } 0}  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "3.102 ns" { countclk theout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "3.102 ns" { countclk countclk~out0 theout } { 0.000ns 0.000ns 1.782ns } { 0.000ns 0.760ns 0.560ns } } } { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "3.102 ns" { countclk fenpincount[4] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "3.102 ns" { countclk countclk~out0 fenpincount[4] } { 0.000ns 0.000ns 1.782ns } { 0.000ns 0.760ns 0.560ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" {  } { { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } {  } 0}  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "3.829 ns" { fenpincount[4] reduce_nor~48 reduce_nor~0 theout~0 theout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "3.829 ns" { fenpincount[4] reduce_nor~48 reduce_nor~0 theout~0 theout } { 0.000ns 0.594ns 0.584ns 0.564ns 0.357ns } { 0.000ns 0.459ns 0.213ns 0.332ns 0.726ns } } } { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "3.102 ns" { countclk theout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "3.102 ns" { countclk countclk~out0 theout } { 0.000ns 0.000ns 1.782ns } { 0.000ns 0.760ns 0.560ns } } } { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "3.102 ns" { countclk fenpincount[4] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "3.102 ns" { countclk countclk~out0 fenpincount[4] } { 0.000ns 0.000ns 1.782ns } { 0.000ns 0.760ns 0.560ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "theout dat\[0\] countclk 4.880 ns register " "Info: tsu for register \"theout\" (data pin = \"dat\[0\]\", clock pin = \"countclk\") is 4.880 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.972 ns + Longest pin register " "Info: + Longest pin to register delay is 7.972 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.141 ns) 1.141 ns dat\[0\] 1 PIN PIN_Y18 2 " "Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_Y18; Fanout = 2; PIN Node = 'dat\[0\]'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "" { dat[0] } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.876 ns) + CELL(0.451 ns) 6.468 ns LessThan~142COUT1_146 2 COMB LC_X34_Y14_N0 1 " "Info: 2: + IC(4.876 ns) + CELL(0.451 ns) = 6.468 ns; Loc. = LC_X34_Y14_N0; Fanout = 1; COMB Node = 'LessThan~142COUT1_146'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "5.327 ns" { dat[0] LessThan~142COUT1_146 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 6.530 ns LessThan~137COUT1_147 3 COMB LC_X34_Y14_N1 1 " "Info: 3: + IC(0.000 ns) + CELL(0.062 ns) = 6.530 ns; Loc. = LC_X34_Y14_N1; Fanout = 1; COMB Node = 'LessThan~137COUT1_147'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "0.062 ns" { LessThan~142COUT1_146 LessThan~137COUT1_147 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 6.592 ns LessThan~132COUT1_148 4 COMB LC_X34_Y14_N2 1 " "Info: 4: + IC(0.000 ns) + CELL(0.062 ns) = 6.592 ns; Loc. = LC_X34_Y14_N2; Fanout = 1; COMB Node = 'LessThan~132COUT1_148'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "0.062 ns" { LessThan~137COUT1_147 LessThan~132COUT1_148 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 6.654 ns LessThan~127COUT1 5 COMB LC_X34_Y14_N3 1 " "Info: 5: + IC(0.000 ns) + CELL(0.062 ns) = 6.654 ns; Loc. = LC_X34_Y14_N3; Fanout = 1; COMB Node = 'LessThan~127COUT1'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "0.062 ns" { LessThan~132COUT1_148 LessThan~127COUT1 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 6.777 ns LessThan~122 6 COMB LC_X34_Y14_N4 1 " "Info: 6: + IC(0.000 ns) + CELL(0.123 ns) = 6.777 ns; Loc. = LC_X34_Y14_N4; Fanout = 1; COMB Node = 'LessThan~122'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "0.123 ns" { LessThan~127COUT1 LessThan~122 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.472 ns) 7.249 ns LessThan~105 7 COMB LC_X34_Y14_N7 1 " "Info: 7: + IC(0.000 ns) + CELL(0.472 ns) = 7.249 ns; Loc. = LC_X34_Y14_N7; Fanout = 1; COMB Node = 'LessThan~105'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "0.472 ns" { LessThan~122 LessThan~105 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.359 ns) + CELL(0.364 ns) 7.972 ns theout 8 REG LC_X34_Y14_N9 1 " "Info: 8: + IC(0.359 ns) + CELL(0.364 ns) = 7.972 ns; Loc. = LC_X34_Y14_N9; Fanout = 1; REG Node = 'theout'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "0.723 ns" { LessThan~105 theout } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.737 ns 34.33 % " "Info: Total cell delay = 2.737 ns ( 34.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.235 ns 65.67 % " "Info: Total interconnect delay = 5.235 ns ( 65.67 % )" {  } {  } 0}  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "7.972 ns" { dat[0] LessThan~142COUT1_146 LessThan~137COUT1_147 LessThan~132COUT1_148 LessThan~127COUT1 LessThan~122 LessThan~105 theout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "7.972 ns" { dat[0] dat[0]~out0 LessThan~142COUT1_146 LessThan~137COUT1_147 LessThan~132COUT1_148 LessThan~127COUT1 LessThan~122 LessThan~105 theout } { 0.000ns 0.000ns 4.876ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.359ns } { 0.000ns 1.141ns 0.451ns 0.062ns 0.062ns 0.062ns 0.123ns 0.472ns 0.364ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } {  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "countclk destination 3.102 ns - Shortest register " "Info: - Shortest clock path from clock \"countclk\" to destination register is 3.102 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns countclk 1 CLK PIN_M24 17 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_M24; Fanout = 17; CLK Node = 'countclk'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "" { countclk } "NODE_NAME" } "" } } { "pwm.vhd" "" { Text "E:/xiaojin/毕业设计文件/pwm/pwm0/pwm.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.782 ns) + CELL(0.560 ns) 3.102 ns theout 2 REG LC_X34_Y14_N9 1 " "Info: 2: + IC(1.782 ns) + CELL(0.560 ns) = 3.102 ns; Loc. = LC_X34_Y14_N9; Fanout = 1; REG Node = 'theout'" {  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "2.342 ns" { countclk theout } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.320 ns 42.55 % " "Info: Total cell delay = 1.320 ns ( 42.55 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.782 ns 57.45 % " "Info: Total interconnect delay = 1.782 ns ( 57.45 % )" {  } {  } 0}  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "3.102 ns" { countclk theout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "3.102 ns" { countclk countclk~out0 theout } { 0.000ns 0.000ns 1.782ns } { 0.000ns 0.760ns 0.560ns } } }  } 0}  } { { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "7.972 ns" { dat[0] LessThan~142COUT1_146 LessThan~137COUT1_147 LessThan~132COUT1_148 LessThan~127COUT1 LessThan~122 LessThan~105 theout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "7.972 ns" { dat[0] dat[0]~out0 LessThan~142COUT1_146 LessThan~137COUT1_147 LessThan~132COUT1_148 LessThan~127COUT1 LessThan~122 LessThan~105 theout } { 0.000ns 0.000ns 4.876ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.359ns } { 0.000ns 1.141ns 0.451ns 0.062ns 0.062ns 0.062ns 0.123ns 0.472ns 0.364ns } } } { "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" "" { Report "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm_cmp.qrpt" Compiler "pwm" "UNKNOWN" "V1" "E:/xiaojin/毕业设计文件/pwm/pwm0/db/pwm.quartus_db" { Floorplan "E:/xiaojin/毕业设计文件/pwm/pwm0/" "" "3.102 ns" { countclk theout } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "3.102 ns" { countclk countclk~out0 theout } { 0.000ns 0.000ns 1.782ns } { 0.000ns 0.760ns 0.560ns } } }  } 0}