pwm.tan.rpt

实现PWM波型....使用VHDL语言

; N/A           ; None        ; -3.568 ns ; rs     ; mycounter[4]   ; countclk ;
; N/A           ; None        ; -3.568 ns ; rs     ; mycounter[5]   ; countclk ;
; N/A           ; None        ; -3.568 ns ; rs     ; mycounter[3]   ; countclk ;
; N/A           ; None        ; -3.568 ns ; rs     ; mycounter[2]   ; countclk ;
; N/A           ; None        ; -3.568 ns ; rs     ; mycounter[1]   ; countclk ;
; N/A           ; None        ; -3.568 ns ; rs     ; mycounter[0]   ; countclk ;
; N/A           ; None        ; -3.853 ns ; rs     ; fenpincount[2] ; countclk ;
; N/A           ; None        ; -3.853 ns ; rs     ; fenpincount[1] ; countclk ;
; N/A           ; None        ; -3.853 ns ; rs     ; fenpincount[0] ; countclk ;
; N/A           ; None        ; -3.853 ns ; rs     ; fenpincount[3] ; countclk ;
; N/A           ; None        ; -3.853 ns ; rs     ; fenpincount[4] ; countclk ;
; N/A           ; None        ; -3.853 ns ; rs     ; fenpincount[5] ; countclk ;
; N/A           ; None        ; -3.853 ns ; rs     ; fenpincount[6] ; countclk ;
; N/A           ; None        ; -3.853 ns ; rs     ; fenpincount[7] ; countclk ;
; N/A           ; None        ; -4.058 ns ; dat[5] ; theout         ; countclk ;
; N/A           ; None        ; -4.110 ns ; rs     ; theout         ; countclk ;
; N/A           ; None        ; -4.180 ns ; dat[3] ; theout         ; countclk ;
; N/A           ; None        ; -4.230 ns ; dat[6] ; theout         ; countclk ;
; N/A           ; None        ; -4.302 ns ; dat[4] ; theout         ; countclk ;
; N/A           ; None        ; -4.433 ns ; dat[1] ; theout         ; countclk ;
; N/A           ; None        ; -4.491 ns ; dat[2] ; theout         ; countclk ;
; N/A           ; None        ; -4.768 ns ; dat[0] ; theout         ; countclk ;
+---------------+-------------+-----------+--------+----------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
    Info: Processing started: Tue May 15 10:27:19 2007
Info: Command: quartus_tan --read_settings_files=on --write_settings_files=off pwm -c pwm --speed=6
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "countclk" is an undefined clock
Info: Clock "countclk" has Internal fmax of 249.07 MHz between source register "fenpincount[4]" and destination register "theout" (period= 4.015 ns)
    Info: + Longest register to register delay is 3.829 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X36_Y14_N4; Fanout = 3; REG Node = 'fenpincount[4]'
        Info: 2: + IC(0.594 ns) + CELL(0.459 ns) = 1.053 ns; Loc. = LC_X35_Y14_N9; Fanout = 1; COMB Node = 'reduce_nor~48'
        Info: 3: + IC(0.584 ns) + CELL(0.213 ns) = 1.850 ns; Loc. = LC_X35_Y14_N8; Fanout = 5; COMB Node = 'reduce_nor~0'
        Info: 4: + IC(0.564 ns) + CELL(0.332 ns) = 2.746 ns; Loc. = LC_X34_Y14_N8; Fanout = 1; COMB Node = 'theout~0'
        Info: 5: + IC(0.357 ns) + CELL(0.726 ns) = 3.829 ns; Loc. = LC_X34_Y14_N9; Fanout = 1; REG Node = 'theout'
        Info: Total cell delay = 1.730 ns ( 45.18 % )
        Info: Total interconnect delay = 2.099 ns ( 54.82 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "countclk" to destination register is 3.102 ns
            Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_M24; Fanout = 17; CLK Node = 'countclk'
            Info: 2: + IC(1.782 ns) + CELL(0.560 ns) = 3.102 ns; Loc. = LC_X34_Y14_N9; Fanout = 1; REG Node = 'theout'
            Info: Total cell delay = 1.320 ns ( 42.55 % )
            Info: Total interconnect delay = 1.782 ns ( 57.45 % )
        Info: - Longest clock path from clock "countclk" to source register is 3.102 ns
            Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_M24; Fanout = 17; CLK Node = 'countclk'
            Info: 2: + IC(1.782 ns) + CELL(0.560 ns) = 3.102 ns; Loc. = LC_X36_Y14_N4; Fanout = 3; REG Node = 'fenpincount[4]'
            Info: Total cell delay = 1.320 ns ( 42.55 % )
            Info: Total interconnect delay = 1.782 ns ( 57.45 % )
    Info: + Micro clock to output delay of source is 0.176 ns
    Info: + Micro setup delay of destination is 0.010 ns
Info: tsu for register "theout" (data pin = "dat[0]", clock pin = "countclk") is 4.880 ns
    Info: + Longest pin to register delay is 7.972 ns
        Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_Y18; Fanout = 2; PIN Node = 'dat[0]'
        Info: 2: + IC(4.876 ns) + CELL(0.451 ns) = 6.468 ns; Loc. = LC_X34_Y14_N0; Fanout = 1; COMB Node = 'LessThan~142COUT1_146'
        Info: 3: + IC(0.000 ns) + CELL(0.062 ns) = 6.530 ns; Loc. = LC_X34_Y14_N1; Fanout = 1; COMB Node = 'LessThan~137COUT1_147'
        Info: 4: + IC(0.000 ns) + CELL(0.062 ns) = 6.592 ns; Loc. = LC_X34_Y14_N2; Fanout = 1; COMB Node = 'LessThan~132COUT1_148'
        Info: 5: + IC(0.000 ns) + CELL(0.062 ns) = 6.654 ns; Loc. = LC_X34_Y14_N3; Fanout = 1; COMB Node = 'LessThan~127COUT1'
        Info: 6: + IC(0.000 ns) + CELL(0.123 ns) = 6.777 ns; Loc. = LC_X34_Y14_N4; Fanout = 1; COMB Node = 'LessThan~122'
        Info: 7: + IC(0.000 ns) + CELL(0.472 ns) = 7.249 ns; Loc. = LC_X34_Y14_N7; Fanout = 1; COMB Node = 'LessThan~105'
        Info: 8: + IC(0.359 ns) + CELL(0.364 ns) = 7.972 ns; Loc. = LC_X34_Y14_N9; Fanout = 1; REG Node = 'theout'
        Info: Total cell delay = 2.737 ns ( 34.33 % )
        Info: Total interconnect delay = 5.235 ns ( 65.67 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock "countclk" to destination register is 3.102 ns
        Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_M24; Fanout = 17; CLK Node = 'countclk'
        Info: 2: + IC(1.782 ns) + CELL(0.560 ns) = 3.102 ns; Loc. = LC_X34_Y14_N9; Fanout = 1; REG Node = 'theout'
        Info: Total cell delay = 1.320 ns ( 42.55 % )
        Info: Total interconnect delay = 1.782 ns ( 57.45 % )
Info: tco from clock "countclk" to destination pin "pwmout" through register "theout" is 7.496 ns
    Info: + Longest clock path from clock "countclk" to source register is 3.102 ns
        Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_M24; Fanout = 17; CLK Node = 'countclk'
        Info: 2: + IC(1.782 ns) + CELL(0.560 ns) = 3.102 ns; Loc. = LC_X34_Y14_N9; Fanout = 1; REG Node = 'theout'
        Info: Total cell delay = 1.320 ns ( 42.55 % )
        Info: Total interconnect delay = 1.782 ns ( 57.45 % )
    Info: + Micro clock to output delay of source is 0.176 ns
    Info: + Longest register to pin delay is 4.218 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y14_N9; Fanout = 1; REG Node = 'theout'
        Info: 2: + IC(1.714 ns) + CELL(2.504 ns) = 4.218 ns; Loc. = PIN_AF17; Fanout = 0; PIN Node = 'pwmout'
        Info: Total cell delay = 2.504 ns ( 59.36 % )
        Info: Total interconnect delay = 1.714 ns ( 40.64 % )
Info: th for register "theout" (data pin = "dat[7]", clock pin = "countclk") is -3.131 ns
    Info: + Longest clock path from clock "countclk" to destination register is 3.102 ns
        Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_M24; Fanout = 17; CLK Node = 'countclk'
        Info: 2: + IC(1.782 ns) + CELL(0.560 ns) = 3.102 ns; Loc. = LC_X34_Y14_N9; Fanout = 1; REG Node = 'theout'
        Info: Total cell delay = 1.320 ns ( 42.55 % )
        Info: Total interconnect delay = 1.782 ns ( 57.45 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 6.333 ns
        Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_AA17; Fanout = 1; PIN Node = 'dat[7]'
        Info: 2: + IC(4.382 ns) + CELL(0.087 ns) = 5.610 ns; Loc. = LC_X34_Y14_N7; Fanout = 1; COMB Node = 'LessThan~105'
        Info: 3: + IC(0.359 ns) + CELL(0.364 ns) = 6.333 ns; Loc. = LC_X34_Y14_N9; Fanout = 1; REG Node = 'theout'
        Info: Total cell delay = 1.592 ns ( 25.14 % )
        Info: Total interconnect delay = 4.741 ns ( 74.86 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue May 15 10:27:21 2007
    Info: Elapsed time: 00:00:02