send_test.txt

输入时钟

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity send_test is
	port(clkin:in std_logic;
	     --valid:in std_logic;
	     valid:out std_logic;
	     --sync: in std_logic;
	     sync: out std_logic;
	     d0,d1,d2,d3,d4,d5,d6,d7:out std_logic_vector(7 downto 0));
end send_test;


architecture launch_arch of send_test is	
	begin	
process(clkin)
    variable i:integer range 0 to 7:=0;
    variable count:integer range 0 to 255:=0;     
	begin 
	if (clkin'event and clkin='1') then
			if count=0 then
			    sync<='1';
			end if;
			if count>0 then
				sync<='0';
	    	end if;
	   d0<=(others=>'0');
	   d1<=(others=>'0');
	   d2<=(others=>'0');
	   d3<=(others=>'0');
	   d4<=(others=>'0');
       d5<=(others=>'0');
	   d6<=(others=>'0');
	   d7<=(others=>'0');
	 if count<188 then
	      valid<='1';
	   	  case i is
	    	when 0 =>
	        	d0<=x"47";
	    	when 1 =>
	        	d1<=x"47";
	    	when 2 =>
	        	d2<=x"47";
	    	when 3 =>
	        	d3<=x"47";
	    	when 4 =>
	        	d4<=x"47";
	    	when 5 =>
	        	d5<=x"47";
	    	when 6 =>
	        	d6<=x"47";
	    	when 7 =>
	        	d7<=x"47";
	     end case;
	end if;
	if count>=188 then
	  	valid<='0';
	end if;
	count:=count+1;  
	i:=i+1;
	end if;
end process;
end launch_arch;