filter.tan.qmsg

vhdl抗抖动滤波器的设计

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register cnt1\[0\] fs_out~reg0 340.02 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 340.02 MHz between source register \"cnt1\[0\]\" and destination register \"fs_out~reg0\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.941 ns " "Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.217 ns + Longest register register " "Info: + Longest register to register delay is 2.217 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt1\[0\] 1 REG LCFF_X27_Y12_N21 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X27_Y12_N21; Fanout = 4; REG Node = 'cnt1\[0\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt1[0] } "NODE_NAME" } } { "Filter.vhd" "" { Text "E:/My_Design/FPGA/Filter/Filter.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.474 ns) + CELL(0.651 ns) 1.125 ns cnt1\[0\]~151 2 COMB LCCOMB_X27_Y12_N26 1 " "Info: 2: + IC(0.474 ns) + CELL(0.651 ns) = 1.125 ns; Loc. = LCCOMB_X27_Y12_N26; Fanout = 1; COMB Node = 'cnt1\[0\]~151'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.125 ns" { cnt1[0] cnt1[0]~151 } "NODE_NAME" } } { "Filter.vhd" "" { Text "E:/My_Design/FPGA/Filter/Filter.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.360 ns) + CELL(0.624 ns) 2.109 ns fs_out~158 3 COMB LCCOMB_X27_Y12_N4 1 " "Info: 3: + IC(0.360 ns) + CELL(0.624 ns) = 2.109 ns; Loc. = LCCOMB_X27_Y12_N4; Fanout = 1; COMB Node = 'fs_out~158'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.984 ns" { cnt1[0]~151 fs_out~158 } "NODE_NAME" } } { "Filter.vhd" "" { Text "E:/My_Design/FPGA/Filter/Filter.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 2.217 ns fs_out~reg0 4 REG LCFF_X27_Y12_N5 2 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 2.217 ns; Loc. = LCFF_X27_Y12_N5; Fanout = 2; REG Node = 'fs_out~reg0'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { fs_out~158 fs_out~reg0 } "NODE_NAME" } } { "Filter.vhd" "" { Text "E:/My_Design/FPGA/Filter/Filter.vhd" 19 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.383 ns ( 62.38 % ) " "Info: Total cell delay = 1.383 ns ( 62.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.834 ns ( 37.62 % ) " "Info: Total interconnect delay = 0.834 ns ( 37.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.217 ns" { cnt1[0] cnt1[0]~151 fs_out~158 fs_out~reg0 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.217 ns" { cnt1[0] {} cnt1[0]~151 {} fs_out~158 {} fs_out~reg0 {} } { 0.000ns 0.474ns 0.360ns 0.000ns } { 0.000ns 0.651ns 0.624ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.809 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.809 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Filter.vhd" "" { Text "E:/My_Design/FPGA/Filter/Filter.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 7 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "Filter.vhd" "" { Text "E:/My_Design/FPGA/Filter/Filter.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.860 ns) + CELL(0.666 ns) 2.809 ns fs_out~reg0 3 REG LCFF_X27_Y12_N5 2 " "Info: 3: + IC(0.860 ns) + CELL(0.666 ns) = 2.809 ns; Loc. = LCFF_X27_Y12_N5; Fanout = 2; REG Node = 'fs_out~reg0'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.526 ns" { clk~clkctrl fs_out~reg0 } "NODE_NAME" } } { "Filter.vhd" "" { Text "E:/My_Design/FPGA/Filter/Filter.vhd" 19 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.29 % ) " "Info: Total cell delay = 1.806 ns ( 64.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.003 ns ( 35.71 % ) " "Info: Total interconnect delay = 1.003 ns ( 35.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.809 ns" { clk clk~clkctrl fs_out~reg0 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.809 ns" { clk {} clk~combout {} clk~clkctrl {} fs_out~reg0 {} } { 0.000ns 0.000ns 0.143ns 0.860ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.809 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.809 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Filter.vhd" "" { Text "E:/My_Design/FPGA/Filter/Filter.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 7 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "Filter.vhd" "" { Text "E:/My_Design/FPGA/Filter/Filter.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.860 ns) + CELL(0.666 ns) 2.809 ns cnt1\[0\] 3 REG LCFF_X27_Y12_N21 4 " "Info: 3: + IC(0.860 ns) + CELL(0.666 ns) = 2.809 ns; Loc. = LCFF_X27_Y12_N21; Fanout = 4; REG Node = 'cnt1\[0\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.526 ns" { clk~clkctrl cnt1[0] } "NODE_NAME" } } { "Filter.vhd" "" { Text "E:/My_Design/FPGA/Filter/Filter.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.29 % ) " "Info: Total cell delay = 1.806 ns ( 64.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.003 ns ( 35.71 % ) " "Info: Total interconnect delay = 1.003 ns ( 35.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.809 ns" { clk clk~clkctrl cnt1[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.809 ns" { clk {} clk~combout {} clk~clkctrl {} cnt1[0] {} } { 0.000ns 0.000ns 0.143ns 0.860ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.809 ns" { clk clk~clkctrl fs_out~reg0 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.809 ns" { clk {} clk~combout {} clk~clkctrl {} fs_out~reg0 {} } { 0.000ns 0.000ns 0.143ns 0.860ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.809 ns" { clk clk~clkctrl cnt1[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.809 ns" { clk {} clk~combout {} clk~clkctrl {} cnt1[0] {} } { 0.000ns 0.000ns 0.143ns 0.860ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "Filter.vhd" "" { Text "E:/My_Design/FPGA/Filter/Filter.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "Filter.vhd" "" { Text "E:/My_Design/FPGA/Filter/Filter.vhd" 19 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.217 ns" { cnt1[0] cnt1[0]~151 fs_out~158 fs_out~reg0 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.217 ns" { cnt1[0] {} cnt1[0]~151 {} fs_out~158 {} fs_out~reg0 {} } { 0.000ns 0.474ns 0.360ns 0.000ns } { 0.000ns 0.651ns 0.624ns 0.108ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.809 ns" { clk clk~clkctrl fs_out~reg0 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.809 ns" { clk {} clk~combout {} clk~clkctrl {} fs_out~reg0 {} } { 0.000ns 0.000ns 0.143ns 0.860ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.809 ns" { clk clk~clkctrl cnt1[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.809 ns" { clk {} clk~combout {} clk~clkctrl {} cnt1[0] {} } { 0.000ns 0.000ns 0.143ns 0.860ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { fs_out~reg0 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { fs_out~reg0 {} } {  } {  } "" } } { "Filter.vhd" "" { Text "E:/My_Design/FPGA/Filter/Filter.vhd" 19 0 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "fs_out~reg0 fs_in clk 5.524 ns register " "Info: tsu for register \"fs_out~reg0\" (data pin = \"fs_in\", clock pin = \"clk\") is 5.524 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.373 ns + Longest pin register " "Info: + Longest pin to register delay is 8.373 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.005 ns) 1.005 ns fs_in 1 PIN PIN_6 7 " "Info: 1: + IC(0.000 ns) + CELL(1.005 ns) = 1.005 ns; Loc. = PIN_6; Fanout = 7; PIN Node = 'fs_in'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { fs_in } "NODE_NAME" } } { "Filter.vhd" "" { Text "E:/My_Design/FPGA/Filter/Filter.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.609 ns) + CELL(0.651 ns) 8.265 ns fs_out~158 2 COMB LCCOMB_X27_Y12_N4 1 " "Info: 2: + IC(6.609 ns) + CELL(0.651 ns) = 8.265 ns; Loc. = LCCOMB_X27_Y12_N4; Fanout = 1; COMB Node = 'fs_out~158'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.260 ns" { fs_in fs_out~158 } "NODE_NAME" } } { "Filter.vhd" "" { Text "E:/My_Design/FPGA/Filter/Filter.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 8.373 ns fs_out~reg0 3 REG LCFF_X27_Y12_N5 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 8.373 ns; Loc. = LCFF_X27_Y12_N5; Fanout = 2; REG Node = 'fs_out~reg0'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { fs_out~158 fs_out~reg0 } "NODE_NAME" } } { "Filter.vhd" "" { Text "E:/My_Design/FPGA/Filter/Filter.vhd" 19 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.764 ns ( 21.07 % ) " "Info: Total cell delay = 1.764 ns ( 21.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.609 ns ( 78.93 % ) " "Info: Total interconnect delay = 6.609 ns ( 78.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.373 ns" { fs_in fs_out~158 fs_out~reg0 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "8.373 ns" { fs_in {} fs_in~combout {} fs_out~158 {} fs_out~reg0 {} } { 0.000ns 0.000ns 6.609ns 0.000ns } { 0.000ns 1.005ns 0.651ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "Filter.vhd" "" { Text "E:/My_Design/FPGA/Filter/Filter.vhd" 19 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.809 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.809 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Filter.vhd" "" { Text "E:/My_Design/FPGA/Filter/Filter.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 7 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "Filter.vhd" "" { Text "E:/My_Design/FPGA/Filter/Filter.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.860 ns) + CELL(0.666 ns) 2.809 ns fs_out~reg0 3 REG LCFF_X27_Y12_N5 2 " "Info: 3: + IC(0.860 ns) + CELL(0.666 ns) = 2.809 ns; Loc. = LCFF_X27_Y12_N5; Fanout = 2; REG Node = 'fs_out~reg0'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.526 ns" { clk~clkctrl fs_out~reg0 } "NODE_NAME" } } { "Filter.vhd" "" { Text "E:/My_Design/FPGA/Filter/Filter.vhd" 19 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.29 % ) " "Info: Total cell delay = 1.806 ns ( 64.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.003 ns ( 35.71 % ) " "Info: Total interconnect delay = 1.003 ns ( 35.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.809 ns" { clk clk~clkctrl fs_out~reg0 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.809 ns" { clk {} clk~combout {} clk~clkctrl {} fs_out~reg0 {} } { 0.000ns 0.000ns 0.143ns 0.860ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.373 ns" { fs_in fs_out~158 fs_out~reg0 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "8.373 ns" { fs_in {} fs_in~combout {} fs_out~158 {} fs_out~reg0 {} } { 0.000ns 0.000ns 6.609ns 0.000ns } { 0.000ns 1.005ns 0.651ns 0.108ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.809 ns" { clk clk~clkctrl fs_out~reg0 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.809 ns" { clk {} clk~combout {} clk~clkctrl {} fs_out~reg0 {} } { 0.000ns 0.000ns 0.143ns 0.860ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk fs_out fs_out~reg0 7.112 ns register " "Info: tco from clock \"clk\" to destination pin \"fs_out\" through register \"fs_out~reg0\" is 7.112 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.809 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.809 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Filter.vhd" "" { Text "E:/My_Design/FPGA/Filter/Filter.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 7 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "Filter.vhd" "" { Text "E:/My_Design/FPGA/Filter/Filter.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.860 ns) + CELL(0.666 ns) 2.809 ns fs_out~reg0 3 REG LCFF_X27_Y12_N5 2 " "Info: 3: + IC(0.860 ns) + CELL(0.666 ns) = 2.809 ns; Loc. = LCFF_X27_Y12_N5; Fanout = 2; REG Node = 'fs_out~reg0'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.526 ns" { clk~clkctrl fs_out~reg0 } "NODE_NAME" } } { "Filter.vhd" "" { Text "E:/My_Design/FPGA/Filter/Filter.vhd" 19 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.29 % ) " "Info: Total cell delay = 1.806 ns ( 64.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.003 ns ( 35.71 % ) " "Info: Total interconnect delay = 1.003 ns ( 35.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.809 ns" { clk clk~clkctrl fs_out~reg0 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.809 ns" { clk {} clk~combout {} clk~clkctrl {} fs_out~reg0 {} } { 0.000ns 0.000ns 0.143ns 0.860ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "Filter.vhd" "" { Text "E:/My_Design/FPGA/Filter/Filter.vhd" 19 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.999 ns + Longest register pin " "Info: + Longest register to pin delay is 3.999 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fs_out~reg0 1 REG LCFF_X27_Y12_N5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X27_Y12_N5; Fanout = 2; REG Node = 'fs_out~reg0'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { fs_out~reg0 } "NODE_NAME" } } { "Filter.vhd" "" { Text "E:/My_Design/FPGA/Filter/Filter.vhd" 19 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.709 ns) + CELL(3.290 ns) 3.999 ns fs_out 2 PIN PIN_151 0 " "Info: 2: + IC(0.709 ns) + CELL(3.290 ns) = 3.999 ns; Loc. = PIN_151; Fanout = 0; PIN Node = 'fs_out'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.999 ns" { fs_out~reg0 fs_out } "NODE_NAME" } } { "Filter.vhd" "" { Text "E:/My_Design/FPGA/Filter/Filter.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.290 ns ( 82.27 % ) " "Info: Total cell delay = 3.290 ns ( 82.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.709 ns ( 17.73 % ) " "Info: Total interconnect delay = 0.709 ns ( 17.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.999 ns" { fs_out~reg0 fs_out } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "3.999 ns" { fs_out~reg0 {} fs_out {} } { 0.000ns 0.709ns } { 0.000ns 3.290ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.809 ns" { clk clk~clkctrl fs_out~reg0 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.809 ns" { clk {} clk~combout {} clk~clkctrl {} fs_out~reg0 {} } { 0.000ns 0.000ns 0.143ns 0.860ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.999 ns" { fs_out~reg0 fs_out } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "3.999 ns" { fs_out~reg0 {} fs_out {} } { 0.000ns 0.709ns } { 0.000ns 3.290ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "cnt1\[1\] fs_in clk -5.141 ns register " "Info: th for register \"cnt1\[1\]\" (data pin = \"fs_in\", clock pin = \"clk\") is -5.141 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.809 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.809 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Filter.vhd" "" { Text "E:/My_Design/FPGA/Filter/Filter.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 7 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "Filter.vhd" "" { Text "E:/My_Design/FPGA/Filter/Filter.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.860 ns) + CELL(0.666 ns) 2.809 ns cnt1\[1\] 3 REG LCFF_X27_Y12_N11 4 " "Info: 3: + IC(0.860 ns) + CELL(0.666 ns) = 2.809 ns; Loc. = LCFF_X27_Y12_N11; Fanout = 4; REG Node = 'cnt1\[1\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.526 ns" { clk~clkctrl cnt1[1] } "NODE_NAME" } } { "Filter.vhd" "" { Text "E:/My_Design/FPGA/Filter/Filter.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.29 % ) " "Info: Total cell delay = 1.806 ns ( 64.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.003 ns ( 35.71 % ) " "Info: Total interconnect delay = 1.003 ns ( 35.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.809 ns" { clk clk~clkctrl cnt1[1] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.809 ns" { clk {} clk~combout {} clk~clkctrl {} cnt1[1] {} } { 0.000ns 0.000ns 0.143ns 0.860ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "Filter.vhd" "" { Text "E:/My_Design/FPGA/Filter/Filter.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.256 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.256 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.005 ns) 1.005 ns fs_in 1 PIN PIN_6 7 " "Info: 1: + IC(0.000 ns) + CELL(1.005 ns) = 1.005 ns; Loc. = PIN_6; Fanout = 7; PIN Node = 'fs_in'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { fs_in } "NODE_NAME" } } { "Filter.vhd" "" { Text "E:/My_Design/FPGA/Filter/Filter.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.609 ns) + CELL(0.534 ns) 8.148 ns cnt1~154 2 COMB LCCOMB_X27_Y12_N10 1 " "Info: 2: + IC(6.609 ns) + CELL(0.534 ns) = 8.148 ns; Loc. = LCCOMB_X27_Y12_N10; Fanout = 1; COMB Node = 'cnt1~154'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.143 ns" { fs_in cnt1~154 } "NODE_NAME" } } { "Filter.vhd" "" { Text "E:/My_Design/FPGA/Filter/Filter.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 8.256 ns cnt1\[1\] 3 REG LCFF_X27_Y12_N11 4 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 8.256 ns; Loc. = LCFF_X27_Y12_N11; Fanout = 4; REG Node = 'cnt1\[1\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { cnt1~154 cnt1[1] } "NODE_NAME" } } { "Filter.vhd" "" { Text "E:/My_Design/FPGA/Filter/Filter.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.647 ns ( 19.95 % ) " "Info: Total cell delay = 1.647 ns ( 19.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.609 ns ( 80.05 % ) " "Info: Total interconnect delay = 6.609 ns ( 80.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.256 ns" { fs_in cnt1~154 cnt1[1] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "8.256 ns" { fs_in {} fs_in~combout {} cnt1~154 {} cnt1[1] {} } { 0.000ns 0.000ns 6.609ns 0.000ns } { 0.000ns 1.005ns 0.534ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.809 ns" { clk clk~clkctrl cnt1[1] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.809 ns" { clk {} clk~combout {} clk~clkctrl {} cnt1[1] {} } { 0.000ns 0.000ns 0.143ns 0.860ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.256 ns" { fs_in cnt1~154 cnt1[1] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "8.256 ns" { fs_in {} fs_in~combout {} cnt1~154 {} cnt1[1] {} } { 0.000ns 0.000ns 6.609ns 0.000ns } { 0.000ns 1.005ns 0.534ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}