freqtest.v

学verilog时写的8位十进制频率计

module freqtest(clock,freq_input,dig,seg,test);
	input clock;               //系统时钟
	input freq_input;         //被测信号
	output[7:0] dig;          //数码管选择输出引脚
	output[7:0] seg;         //数码管段输出引脚
	output[9:0] test;       //输出频率信号，用于测试
	reg[25:0] counter;
	reg[31:0] freq_result;
	reg[31:0] pre_freq;
	reg rst;
	wire  divide_clk;
	wire  clk_scan;
	wire cout1,cout2,cout3,cout4,cout5,cout6,cout7;
	assign clk_scan=counter[15];
	assign test=counter[9:0];
	
	//时钟分频进程，分出1HZ基准信号
	always@(posedge clock)
		begin
			if(divide_clk)
				counter<=26'd0;
			else 
			
				counter<=counter+1'b1;
		end
	assign divide_clk=(counter>=26'd48000000);
	//锁存测量进程
	always@(posedge clock)
		begin
			if(divide_clk)
				freq_result<=pre_freq;
		end
	//产生计数器复位信号
    always@(posedge clock)
		begin
			if(divide_clk)
				rst<=1'b1;
			else 
				rst<=1'b0;
		end
	cnt10 u1(.clock(freq_input),.rst(rst),.cin(1'b1),.cout(cout1),.dout(pre_freq[3:0]));	
	cnt10 u2(.clock(freq_input),.rst(rst),.cin(1'b1),.cout(cout2),.dout(pre_freq[7:4]));
	cnt10 u3(.clock(freq_input),.rst(rst),.cin(1'b1),.cout(cout3),.dout(pre_freq[11:8]));
	cnt10 u4(.clock(freq_input),.rst(rst),.cin(1'b1),.cout(cout4),.dout(pre_freq[15:12]));
	cnt10 u5(.clock(freq_input),.rst(rst),.cin(1'b1),.cout(cout5),.dout(pre_freq[19:16]));
	cnt10 u6(.clock(freq_input),.rst(rst),.cin(1'b1),.cout(cout6),.dout(pre_freq[23:20]));
	cnt10 u7(.clock(freq_input),.rst(rst),.cin(1'b1),.cout(cout7),.dout(pre_freq[27:24]));
	cnt10 u8(.clock(freq_input),.rst(rst),.cin(1'b1),.cout(cout7),.dout(pre_freq[31:28]));	
	//数码管显示模块
	scan_led u9(.clk_lk(clk_scan),.d(freq_result),.dig(dig),.seg(seg));	
endmodule