📄 cnt10b.tan.qmsg
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{ "Info" "ITDB_FULL_TPD_RESULT" "we clkout 15.000 ns Longest " "Info: Longest tpd from source pin \"we\" to destination pin \"clkout\" is 15.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns we 1 CLK PIN_81 6 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_81; Fanout = 6; CLK Node = 'we'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "" { we } "NODE_NAME" } "" } } { "cnt10b.vhd" "" { Text "D:/CNT10B/cnt10b.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 11.000 ns clk0~27 2 COMB LC19 1 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC19; Fanout = 1; COMB Node = 'clk0~27'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "9.000 ns" { we clk0~27 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 15.000 ns clkout 3 PIN PIN_21 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 15.000 ns; Loc. = PIN_21; Fanout = 0; PIN Node = 'clkout'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "4.000 ns" { clk0~27 clkout } "NODE_NAME" } "" } } { "cnt10b.vhd" "" { Text "D:/CNT10B/cnt10b.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.000 ns ( 86.67 % ) " "Info: Total cell delay = 13.000 ns ( 86.67 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 13.33 % ) " "Info: Total interconnect delay = 2.000 ns ( 13.33 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "15.000 ns" { we clk0~27 clkout } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "15.000 ns" { we we~out clk0~27 clkout } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 7.000ns 4.000ns } } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 30 15:51:02 2008 " "Info: Processing ended: Wed Apr 30 15:51:02 2008" { } { } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
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