📄 cnt10b.tan.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "we register lpm_counter:cqi_rtl_0\|dffs\[0\] register lpm_counter:cqi_rtl_0\|dffs\[8\] 76.92 MHz 13.0 ns Internal " "Info: Clock \"we\" has Internal fmax of 76.92 MHz between source register \"lpm_counter:cqi_rtl_0\|dffs\[0\]\" and destination register \"lpm_counter:cqi_rtl_0\|dffs\[8\]\" (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:cqi_rtl_0\|dffs\[0\] 1 REG LC17 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC17; Fanout = 10; REG Node = 'lpm_counter:cqi_rtl_0\|dffs\[0\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "" { lpm_counter:cqi_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns lpm_counter:cqi_rtl_0\|dffs\[8\] 2 REG LC3 2 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC3; Fanout = 2; REG Node = 'lpm_counter:cqi_rtl_0\|dffs\[8\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "8.000 ns" { lpm_counter:cqi_rtl_0|dffs[0] lpm_counter:cqi_rtl_0|dffs[8] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns ( 75.00 % ) " "Info: Total cell delay = 6.000 ns ( 75.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 25.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "8.000 ns" { lpm_counter:cqi_rtl_0|dffs[0] lpm_counter:cqi_rtl_0|dffs[8] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.000 ns" { lpm_counter:cqi_rtl_0|dffs[0] lpm_counter:cqi_rtl_0|dffs[8] } { 0.000ns 2.000ns } { 0.000ns 6.000ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "we destination 18.000 ns + Shortest register " "Info: + Shortest clock path from clock \"we\" to destination register is 18.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns we 1 CLK PIN_81 6 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_81; Fanout = 6; CLK Node = 'we'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "" { we } "NODE_NAME" } "" } } { "cnt10b.vhd" "" { Text "D:/CNT10B/cnt10b.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(8.000 ns) 12.000 ns clk0~46 2 COMB SEXP3 8 " "Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP3; Fanout = 8; COMB Node = 'clk0~46'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "10.000 ns" { we clk0~46 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.000 ns) 18.000 ns lpm_counter:cqi_rtl_0\|dffs\[8\] 3 REG LC3 2 " "Info: 3: + IC(0.000 ns) + CELL(6.000 ns) = 18.000 ns; Loc. = LC3; Fanout = 2; REG Node = 'lpm_counter:cqi_rtl_0\|dffs\[8\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "6.000 ns" { clk0~46 lpm_counter:cqi_rtl_0|dffs[8] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "16.000 ns ( 88.89 % ) " "Info: Total cell delay = 16.000 ns ( 88.89 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 11.11 % ) " "Info: Total interconnect delay = 2.000 ns ( 11.11 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "18.000 ns" { we clk0~46 lpm_counter:cqi_rtl_0|dffs[8] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "18.000 ns" { we we~out clk0~46 lpm_counter:cqi_rtl_0|dffs[8] } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 8.000ns 6.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "we source 18.000 ns - Longest register " "Info: - Longest clock path from clock \"we\" to source register is 18.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns we 1 CLK PIN_81 6 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_81; Fanout = 6; CLK Node = 'we'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "" { we } "NODE_NAME" } "" } } { "cnt10b.vhd" "" { Text "D:/CNT10B/cnt10b.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(8.000 ns) 12.000 ns clk0~28 2 COMB SEXP19 1 " "Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP19; Fanout = 1; COMB Node = 'clk0~28'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "10.000 ns" { we clk0~28 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.000 ns) 18.000 ns lpm_counter:cqi_rtl_0\|dffs\[0\] 3 REG LC17 10 " "Info: 3: + IC(0.000 ns) + CELL(6.000 ns) = 18.000 ns; Loc. = LC17; Fanout = 10; REG Node = 'lpm_counter:cqi_rtl_0\|dffs\[0\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "6.000 ns" { clk0~28 lpm_counter:cqi_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "16.000 ns ( 88.89 % ) " "Info: Total cell delay = 16.000 ns ( 88.89 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 11.11 % ) " "Info: Total interconnect delay = 2.000 ns ( 11.11 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "18.000 ns" { we clk0~28 lpm_counter:cqi_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "18.000 ns" { we we~out clk0~28 lpm_counter:cqi_rtl_0|dffs[0] } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 8.000ns 6.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "18.000 ns" { we clk0~46 lpm_counter:cqi_rtl_0|dffs[8] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "18.000 ns" { we we~out clk0~46 lpm_counter:cqi_rtl_0|dffs[8] } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 8.000ns 6.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "18.000 ns" { we clk0~28 lpm_counter:cqi_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "18.000 ns" { we we~out clk0~28 lpm_counter:cqi_rtl_0|dffs[0] } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 8.000ns 6.000ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" { } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "8.000 ns" { lpm_counter:cqi_rtl_0|dffs[0] lpm_counter:cqi_rtl_0|dffs[8] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.000 ns" { lpm_counter:cqi_rtl_0|dffs[0] lpm_counter:cqi_rtl_0|dffs[8] } { 0.000ns 2.000ns } { 0.000ns 6.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "18.000 ns" { we clk0~46 lpm_counter:cqi_rtl_0|dffs[8] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "18.000 ns" { we we~out clk0~46 lpm_counter:cqi_rtl_0|dffs[8] } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 8.000ns 6.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "18.000 ns" { we clk0~28 lpm_counter:cqi_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "18.000 ns" { we we~out clk0~28 lpm_counter:cqi_rtl_0|dffs[0] } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 8.000ns 6.000ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lpm_counter:cqi_rtl_0\|dffs\[0\] register lpm_counter:cqi_rtl_0\|dffs\[8\] 76.92 MHz 13.0 ns Internal " "Info: Clock \"clk\" has Internal fmax of 76.92 MHz between source register \"lpm_counter:cqi_rtl_0\|dffs\[0\]\" and destination register \"lpm_counter:cqi_rtl_0\|dffs\[8\]\" (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:cqi_rtl_0\|dffs\[0\] 1 REG LC17 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC17; Fanout = 10; REG Node = 'lpm_counter:cqi_rtl_0\|dffs\[0\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "" { lpm_counter:cqi_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns lpm_counter:cqi_rtl_0\|dffs\[8\] 2 REG LC3 2 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC3; Fanout = 2; REG Node = 'lpm_counter:cqi_rtl_0\|dffs\[8\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "8.000 ns" { lpm_counter:cqi_rtl_0|dffs[0] lpm_counter:cqi_rtl_0|dffs[8] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns ( 75.00 % ) " "Info: Total cell delay = 6.000 ns ( 75.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 25.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "8.000 ns" { lpm_counter:cqi_rtl_0|dffs[0] lpm_counter:cqi_rtl_0|dffs[8] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.000 ns" { lpm_counter:cqi_rtl_0|dffs[0] lpm_counter:cqi_rtl_0|dffs[8] } { 0.000ns 2.000ns } { 0.000ns 6.000ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 18.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 18.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_52 3 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_52; Fanout = 3; CLK Node = 'clk'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "" { clk } "NODE_NAME" } "" } } { "cnt10b.vhd" "" { Text "D:/CNT10B/cnt10b.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(8.000 ns) 12.000 ns clk0~46 2 COMB SEXP3 8 " "Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP3; Fanout = 8; COMB Node = 'clk0~46'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "10.000 ns" { clk clk0~46 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.000 ns) 18.000 ns lpm_counter:cqi_rtl_0\|dffs\[8\] 3 REG LC3 2 " "Info: 3: + IC(0.000 ns) + CELL(6.000 ns) = 18.000 ns; Loc. = LC3; Fanout = 2; REG Node = 'lpm_counter:cqi_rtl_0\|dffs\[8\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "6.000 ns" { clk0~46 lpm_counter:cqi_rtl_0|dffs[8] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "16.000 ns ( 88.89 % ) " "Info: Total cell delay = 16.000 ns ( 88.89 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 11.11 % ) " "Info: Total interconnect delay = 2.000 ns ( 11.11 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "18.000 ns" { clk clk0~46 lpm_counter:cqi_rtl_0|dffs[8] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "18.000 ns" { clk clk~out clk0~46 lpm_counter:cqi_rtl_0|dffs[8] } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 8.000ns 6.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 18.000 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 18.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_52 3 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_52; Fanout = 3; CLK Node = 'clk'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "" { clk } "NODE_NAME" } "" } } { "cnt10b.vhd" "" { Text "D:/CNT10B/cnt10b.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(8.000 ns) 12.000 ns clk0~28 2 COMB SEXP19 1 " "Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP19; Fanout = 1; COMB Node = 'clk0~28'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "10.000 ns" { clk clk0~28 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.000 ns) 18.000 ns lpm_counter:cqi_rtl_0\|dffs\[0\] 3 REG LC17 10 " "Info: 3: + IC(0.000 ns) + CELL(6.000 ns) = 18.000 ns; Loc. = LC17; Fanout = 10; REG Node = 'lpm_counter:cqi_rtl_0\|dffs\[0\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "6.000 ns" { clk0~28 lpm_counter:cqi_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "16.000 ns ( 88.89 % ) " "Info: Total cell delay = 16.000 ns ( 88.89 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 11.11 % ) " "Info: Total interconnect delay = 2.000 ns ( 11.11 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "18.000 ns" { clk clk0~28 lpm_counter:cqi_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "18.000 ns" { clk clk~out clk0~28 lpm_counter:cqi_rtl_0|dffs[0] } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 8.000ns 6.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "18.000 ns" { clk clk0~46 lpm_counter:cqi_rtl_0|dffs[8] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "18.000 ns" { clk clk~out clk0~46 lpm_counter:cqi_rtl_0|dffs[8] } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 8.000ns 6.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "18.000 ns" { clk clk0~28 lpm_counter:cqi_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "18.000 ns" { clk clk~out clk0~28 lpm_counter:cqi_rtl_0|dffs[0] } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 8.000ns 6.000ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" { } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "8.000 ns" { lpm_counter:cqi_rtl_0|dffs[0] lpm_counter:cqi_rtl_0|dffs[8] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.000 ns" { lpm_counter:cqi_rtl_0|dffs[0] lpm_counter:cqi_rtl_0|dffs[8] } { 0.000ns 2.000ns } { 0.000ns 6.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "18.000 ns" { clk clk0~46 lpm_counter:cqi_rtl_0|dffs[8] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "18.000 ns" { clk clk~out clk0~46 lpm_counter:cqi_rtl_0|dffs[8] } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 8.000ns 6.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "18.000 ns" { clk clk0~28 lpm_counter:cqi_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "18.000 ns" { clk clk~out clk0~28 lpm_counter:cqi_rtl_0|dffs[0] } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 8.000ns 6.000ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "lock0 register lpm_counter:cqi_rtl_0\|dffs\[0\] register lpm_counter:cqi_rtl_0\|dffs\[8\] 76.92 MHz 13.0 ns Internal " "Info: Clock \"lock0\" has Internal fmax of 76.92 MHz between source register \"lpm_counter:cqi_rtl_0\|dffs\[0\]\" and destination register \"lpm_counter:cqi_rtl_0\|dffs\[8\]\" (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:cqi_rtl_0\|dffs\[0\] 1 REG LC17 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC17; Fanout = 10; REG Node = 'lpm_counter:cqi_rtl_0\|dffs\[0\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "" { lpm_counter:cqi_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns lpm_counter:cqi_rtl_0\|dffs\[8\] 2 REG LC3 2 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC3; Fanout = 2; REG Node = 'lpm_counter:cqi_rtl_0\|dffs\[8\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "8.000 ns" { lpm_counter:cqi_rtl_0|dffs[0] lpm_counter:cqi_rtl_0|dffs[8] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns ( 75.00 % ) " "Info: Total cell delay = 6.000 ns ( 75.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 25.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "8.000 ns" { lpm_counter:cqi_rtl_0|dffs[0] lpm_counter:cqi_rtl_0|dffs[8] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.000 ns" { lpm_counter:cqi_rtl_0|dffs[0] lpm_counter:cqi_rtl_0|dffs[8] } { 0.000ns 2.000ns } { 0.000ns 6.000ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "lock0 destination 18.000 ns + Shortest register " "Info: + Shortest clock path from clock \"lock0\" to destination register is 18.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns lock0 1 CLK PIN_24 3 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_24; Fanout = 3; CLK Node = 'lock0'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "" { lock0 } "NODE_NAME" } "" } } { "cnt10b.vhd" "" { Text "D:/CNT10B/cnt10b.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(8.000 ns) 12.000 ns clk0~47 2 COMB SEXP5 8 " "Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP5; Fanout = 8; COMB Node = 'clk0~47'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "10.000 ns" { lock0 clk0~47 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.000 ns) 18.000 ns lpm_counter:cqi_rtl_0\|dffs\[8\] 3 REG LC3 2 " "Info: 3: + IC(0.000 ns) + CELL(6.000 ns) = 18.000 ns; Loc. = LC3; Fanout = 2; REG Node = 'lpm_counter:cqi_rtl_0\|dffs\[8\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "6.000 ns" { clk0~47 lpm_counter:cqi_rtl_0|dffs[8] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "16.000 ns ( 88.89 % ) " "Info: Total cell delay = 16.000 ns ( 88.89 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 11.11 % ) " "Info: Total interconnect delay = 2.000 ns ( 11.11 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "18.000 ns" { lock0 clk0~47 lpm_counter:cqi_rtl_0|dffs[8] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "18.000 ns" { lock0 lock0~out clk0~47 lpm_counter:cqi_rtl_0|dffs[8] } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 8.000ns 6.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "lock0 source 18.000 ns - Longest register " "Info: - Longest clock path from clock \"lock0\" to source register is 18.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns lock0 1 CLK PIN_24 3 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_24; Fanout = 3; CLK Node = 'lock0'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "" { lock0 } "NODE_NAME" } "" } } { "cnt10b.vhd" "" { Text "D:/CNT10B/cnt10b.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(8.000 ns) 12.000 ns clk0~29 2 COMB SEXP17 1 " "Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'clk0~29'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "10.000 ns" { lock0 clk0~29 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.000 ns) 18.000 ns lpm_counter:cqi_rtl_0\|dffs\[0\] 3 REG LC17 10 " "Info: 3: + IC(0.000 ns) + CELL(6.000 ns) = 18.000 ns; Loc. = LC17; Fanout = 10; REG Node = 'lpm_counter:cqi_rtl_0\|dffs\[0\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "6.000 ns" { clk0~29 lpm_counter:cqi_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "16.000 ns ( 88.89 % ) " "Info: Total cell delay = 16.000 ns ( 88.89 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 11.11 % ) " "Info: Total interconnect delay = 2.000 ns ( 11.11 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "18.000 ns" { lock0 clk0~29 lpm_counter:cqi_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "18.000 ns" { lock0 lock0~out clk0~29 lpm_counter:cqi_rtl_0|dffs[0] } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 8.000ns 6.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "18.000 ns" { lock0 clk0~47 lpm_counter:cqi_rtl_0|dffs[8] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "18.000 ns" { lock0 lock0~out clk0~47 lpm_counter:cqi_rtl_0|dffs[8] } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 8.000ns 6.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "18.000 ns" { lock0 clk0~29 lpm_counter:cqi_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "18.000 ns" { lock0 lock0~out clk0~29 lpm_counter:cqi_rtl_0|dffs[0] } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 8.000ns 6.000ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" { } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "8.000 ns" { lpm_counter:cqi_rtl_0|dffs[0] lpm_counter:cqi_rtl_0|dffs[8] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.000 ns" { lpm_counter:cqi_rtl_0|dffs[0] lpm_counter:cqi_rtl_0|dffs[8] } { 0.000ns 2.000ns } { 0.000ns 6.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "18.000 ns" { lock0 clk0~47 lpm_counter:cqi_rtl_0|dffs[8] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "18.000 ns" { lock0 lock0~out clk0~47 lpm_counter:cqi_rtl_0|dffs[8] } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 8.000ns 6.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "18.000 ns" { lock0 clk0~29 lpm_counter:cqi_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "18.000 ns" { lock0 lock0~out clk0~29 lpm_counter:cqi_rtl_0|dffs[0] } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 8.000ns 6.000ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "lock0 dout\[8\] lpm_counter:cqi_rtl_0\|dffs\[8\] 23.000 ns register " "Info: tco from clock \"lock0\" to destination pin \"dout\[8\]\" through register \"lpm_counter:cqi_rtl_0\|dffs\[8\]\" is 23.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "lock0 source 18.000 ns + Longest register " "Info: + Longest clock path from clock \"lock0\" to source register is 18.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns lock0 1 CLK PIN_24 3 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_24; Fanout = 3; CLK Node = 'lock0'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "" { lock0 } "NODE_NAME" } "" } } { "cnt10b.vhd" "" { Text "D:/CNT10B/cnt10b.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(8.000 ns) 12.000 ns clk0~47 2 COMB SEXP5 8 " "Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP5; Fanout = 8; COMB Node = 'clk0~47'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "10.000 ns" { lock0 clk0~47 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.000 ns) 18.000 ns lpm_counter:cqi_rtl_0\|dffs\[8\] 3 REG LC3 2 " "Info: 3: + IC(0.000 ns) + CELL(6.000 ns) = 18.000 ns; Loc. = LC3; Fanout = 2; REG Node = 'lpm_counter:cqi_rtl_0\|dffs\[8\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "6.000 ns" { clk0~47 lpm_counter:cqi_rtl_0|dffs[8] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "16.000 ns ( 88.89 % ) " "Info: Total cell delay = 16.000 ns ( 88.89 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 11.11 % ) " "Info: Total interconnect delay = 2.000 ns ( 11.11 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "18.000 ns" { lock0 clk0~47 lpm_counter:cqi_rtl_0|dffs[8] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "18.000 ns" { lock0 lock0~out clk0~47 lpm_counter:cqi_rtl_0|dffs[8] } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 8.000ns 6.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Longest register pin " "Info: + Longest register to pin delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:cqi_rtl_0\|dffs\[8\] 1 REG LC3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 2; REG Node = 'lpm_counter:cqi_rtl_0\|dffs\[8\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "" { lpm_counter:cqi_rtl_0|dffs[8] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 4.000 ns dout\[8\] 2 PIN PIN_12 0 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'dout\[8\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "4.000 ns" { lpm_counter:cqi_rtl_0|dffs[8] dout[8] } "NODE_NAME" } "" } } { "cnt10b.vhd" "" { Text "D:/CNT10B/cnt10b.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns ( 100.00 % ) " "Info: Total cell delay = 4.000 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "4.000 ns" { lpm_counter:cqi_rtl_0|dffs[8] dout[8] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.000 ns" { lpm_counter:cqi_rtl_0|dffs[8] dout[8] } { 0.000ns 0.000ns } { 0.000ns 4.000ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "18.000 ns" { lock0 clk0~47 lpm_counter:cqi_rtl_0|dffs[8] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "18.000 ns" { lock0 lock0~out clk0~47 lpm_counter:cqi_rtl_0|dffs[8] } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 8.000ns 6.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt10b" "UNKNOWN" "V1" "D:/CNT10B/db/cnt10b.quartus_db" { Floorplan "D:/CNT10B/" "" "4.000 ns" { lpm_counter:cqi_rtl_0|dffs[8] dout[8] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.000 ns" { lpm_counter:cqi_rtl_0|dffs[8] dout[8] } { 0.000ns 0.000ns } { 0.000ns 4.000ns } } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
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