cnt10b.tan.rpt

通过ADC0809对模拟信号进行采样

Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "we" is an undefined clock
    Info: Assuming node "clk" is an undefined clock
    Info: Assuming node "lock0" is an undefined clock
Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock "clk0~47" as buffer
    Info: Detected gated clock "clk0~46" as buffer
    Info: Detected gated clock "clk0~29" as buffer
    Info: Detected gated clock "clk0~28" as buffer
Info: Clock "we" has Internal fmax of 76.92 MHz between source register "lpm_counter:cqi_rtl_0|dffs[0]" and destination register "lpm_counter:cqi_rtl_0|dffs[8]" (period= 13.0 ns)
    Info: + Longest register to register delay is 8.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC17; Fanout = 10; REG Node = 'lpm_counter:cqi_rtl_0|dffs[0]'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC3; Fanout = 2; REG Node = 'lpm_counter:cqi_rtl_0|dffs[8]'
        Info: Total cell delay = 6.000 ns ( 75.00 % )
        Info: Total interconnect delay = 2.000 ns ( 25.00 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "we" to destination register is 18.000 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_81; Fanout = 6; CLK Node = 'we'
            Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP3; Fanout = 8; COMB Node = 'clk0~46'
            Info: 3: + IC(0.000 ns) + CELL(6.000 ns) = 18.000 ns; Loc. = LC3; Fanout = 2; REG Node = 'lpm_counter:cqi_rtl_0|dffs[8]'
            Info: Total cell delay = 16.000 ns ( 88.89 % )
            Info: Total interconnect delay = 2.000 ns ( 11.11 % )
        Info: - Longest clock path from clock "we" to source register is 18.000 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_81; Fanout = 6; CLK Node = 'we'
            Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP19; Fanout = 1; COMB Node = 'clk0~28'
            Info: 3: + IC(0.000 ns) + CELL(6.000 ns) = 18.000 ns; Loc. = LC17; Fanout = 10; REG Node = 'lpm_counter:cqi_rtl_0|dffs[0]'
            Info: Total cell delay = 16.000 ns ( 88.89 % )
            Info: Total interconnect delay = 2.000 ns ( 11.11 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Info: Clock "clk" has Internal fmax of 76.92 MHz between source register "lpm_counter:cqi_rtl_0|dffs[0]" and destination register "lpm_counter:cqi_rtl_0|dffs[8]" (period= 13.0 ns)
    Info: + Longest register to register delay is 8.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC17; Fanout = 10; REG Node = 'lpm_counter:cqi_rtl_0|dffs[0]'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC3; Fanout = 2; REG Node = 'lpm_counter:cqi_rtl_0|dffs[8]'
        Info: Total cell delay = 6.000 ns ( 75.00 % )
        Info: Total interconnect delay = 2.000 ns ( 25.00 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 18.000 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_52; Fanout = 3; CLK Node = 'clk'
            Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP3; Fanout = 8; COMB Node = 'clk0~46'
            Info: 3: + IC(0.000 ns) + CELL(6.000 ns) = 18.000 ns; Loc. = LC3; Fanout = 2; REG Node = 'lpm_counter:cqi_rtl_0|dffs[8]'
            Info: Total cell delay = 16.000 ns ( 88.89 % )
            Info: Total interconnect delay = 2.000 ns ( 11.11 % )
        Info: - Longest clock path from clock "clk" to source register is 18.000 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_52; Fanout = 3; CLK Node = 'clk'
            Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP19; Fanout = 1; COMB Node = 'clk0~28'
            Info: 3: + IC(0.000 ns) + CELL(6.000 ns) = 18.000 ns; Loc. = LC17; Fanout = 10; REG Node = 'lpm_counter:cqi_rtl_0|dffs[0]'
            Info: Total cell delay = 16.000 ns ( 88.89 % )
            Info: Total interconnect delay = 2.000 ns ( 11.11 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Info: Clock "lock0" has Internal fmax of 76.92 MHz between source register "lpm_counter:cqi_rtl_0|dffs[0]" and destination register "lpm_counter:cqi_rtl_0|dffs[8]" (period= 13.0 ns)
    Info: + Longest register to register delay is 8.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC17; Fanout = 10; REG Node = 'lpm_counter:cqi_rtl_0|dffs[0]'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC3; Fanout = 2; REG Node = 'lpm_counter:cqi_rtl_0|dffs[8]'
        Info: Total cell delay = 6.000 ns ( 75.00 % )
        Info: Total interconnect delay = 2.000 ns ( 25.00 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "lock0" to destination register is 18.000 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_24; Fanout = 3; CLK Node = 'lock0'
            Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP5; Fanout = 8; COMB Node = 'clk0~47'
            Info: 3: + IC(0.000 ns) + CELL(6.000 ns) = 18.000 ns; Loc. = LC3; Fanout = 2; REG Node = 'lpm_counter:cqi_rtl_0|dffs[8]'
            Info: Total cell delay = 16.000 ns ( 88.89 % )
            Info: Total interconnect delay = 2.000 ns ( 11.11 % )
        Info: - Longest clock path from clock "lock0" to source register is 18.000 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_24; Fanout = 3; CLK Node = 'lock0'
            Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'clk0~29'
            Info: 3: + IC(0.000 ns) + CELL(6.000 ns) = 18.000 ns; Loc. = LC17; Fanout = 10; REG Node = 'lpm_counter:cqi_rtl_0|dffs[0]'
            Info: Total cell delay = 16.000 ns ( 88.89 % )
            Info: Total interconnect delay = 2.000 ns ( 11.11 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Info: tco from clock "lock0" to destination pin "dout[8]" through register "lpm_counter:cqi_rtl_0|dffs[8]" is 23.000 ns
    Info: + Longest clock path from clock "lock0" to source register is 18.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_24; Fanout = 3; CLK Node = 'lock0'
        Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP5; Fanout = 8; COMB Node = 'clk0~47'
        Info: 3: + IC(0.000 ns) + CELL(6.000 ns) = 18.000 ns; Loc. = LC3; Fanout = 2; REG Node = 'lpm_counter:cqi_rtl_0|dffs[8]'
        Info: Total cell delay = 16.000 ns ( 88.89 % )
        Info: Total interconnect delay = 2.000 ns ( 11.11 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Longest register to pin delay is 4.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 2; REG Node = 'lpm_counter:cqi_rtl_0|dffs[8]'
        Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'dout[8]'
        Info: Total cell delay = 4.000 ns ( 100.00 % )
Info: Longest tpd from source pin "we" to destination pin "clkout" is 15.000 ns
    Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_81; Fanout = 6; CLK Node = 'we'
    Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC19; Fanout = 1; COMB Node = 'clk0~27'
    Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 15.000 ns; Loc. = PIN_21; Fanout = 0; PIN Node = 'clkout'
    Info: Total cell delay = 13.000 ns ( 86.67 % )
    Info: Total interconnect delay = 2.000 ns ( 13.33 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Processing ended: Wed Apr 30 15:51:02 2008
    Info: Elapsed time: 00:00:01