📄 cnt10b.map.talkback.xml

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<!--
This XML file (created on Wed Apr 30 15:50:56 2008) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to license.txt.
-->
<talkback>
<ver>5.1</ver>
<schema>quartus_version_5.1_build_176.xsd</schema><license>
	<host_id>0015c563ebaf</host_id>
	<nic_id>001302a85905</nic_id>
	<cdrive_id>6c0f603a</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>5.1</version>
	<build>Build 176</build>
	<binary_type>32</binary_type>
	<module>quartus_map.exe</module>
	<edition>Full Version</edition>
	<compilation_end_time>Wed Apr 30 15:50:56 2008</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>2</proc_count>
		<cpu_freq units="MHz">1596</cpu_freq>
	</cpu>
	<ram units="MB">503</ram>
</machine>
<top_file>D:/CNT10B/cnt10b</top_file>
<mep_data>
	<command_line>quartus_map --read_settings_files=on --write_settings_files=off cnt10b -c cnt10b</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<messages>
	<warning>Warning: Using design file cnt10b.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project</warning>
	<info>Info: Quartus II Analysis &amp; Synthesis was successful. 0 errors, 1 warning</info>
	<info>Info: Elapsed time: 00:00:02</info>
	<info>Info: Processing ended: Wed Apr 30 15:50:56 2008</info>
	<info>Info: Implemented 26 device resources after synthesis - the final resource count might be different</info>
	<info>Info: Implemented 2 shareable expanders</info>
</messages>
<analysis___synthesis_settings>
	<row>
		<option>Device</option>
		<setting>EPM7128SLC84-15</setting>
	</row>
	<row>
		<option>Top-level entity name</option>
		<setting>cnt10b</setting>
		<default_value>cnt10b</default_value>
	</row>
	<row>
		<option>Family name</option>
		<setting>MAX7000S</setting>
		<default_value>Stratix</default_value>
	</row>
	<row>
		<option>Use smart compilation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Create Debugging Nodes for IP Cores</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Preserve fewer node names</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Disable OpenCore Plus hardware evaluation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Verilog Version</option>
		<setting>Verilog_2001</setting>
		<default_value>Verilog_2001</default_value>
	</row>
	<row>
		<option>VHDL Version</option>
		<setting>VHDL93</setting>
		<default_value>VHDL93</default_value>
	</row>
	<row>
		<option>State Machine Processing</option>
		<setting>Auto</setting>
		<default_value>Auto</default_value>
	</row>
	<row>
		<option>Extract Verilog State Machines</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Extract VHDL State Machines</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Add Pass-Through Logic to Inferred RAMs</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>NOT Gate Push-Back</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Power-Up Don&apos;t Care</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Remove Redundant Logic Cells</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Remove Duplicate Registers</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Ignore CARRY Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore CASCADE Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore GLOBAL Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore ROW GLOBAL Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A</option>
		<setting>Auto</setting>
		<default_value>Auto</default_value>
	</row>
	<row>
		<option>Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Limit AHDL Integers to 32 Bits</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Optimization Technique -- MAX 7000B/7000AE/3000A/7000S/7000A</option>
		<setting>Speed</setting>
		<default_value>Speed</default_value>
	</row>
	<row>
		<option>Allow XOR Gate Usage</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Logic Cell Insertion</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A</option>
		<setting>4</setting>
		<default_value>4</default_value>
	</row>
	<row>
		<option>Auto Parallel Expanders</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Open-Drain Pins</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Remove Duplicate Logic</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Resource Sharing</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Maximum Fan-in Per Macrocell -- MAX 7000B/7000AE/3000A/7000S/7000A</option>
		<setting>100</setting>
		<default_value>100</default_value>
	</row>
	<row>
		<option>Ignore translate_off and translate_on Synthesis Directives</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Show Parameter Settings Tables in Synthesis Report</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>HDL message level</option>
		<setting>Level2</setting>
		<default_value>Level2</default_value>
	</row>
</analysis___synthesis_settings>
<compilation_summary>
	<flow_status>Successful - Wed Apr 30 15:50:56 2008</flow_status>
	<quartus_ii_version>5.1 Build 176 10/26/2005 SJ Web Edition</quartus_ii_version>
	<revision_name>cnt10b</revision_name>
	<top_level_entity_name>cnt10b</top_level_entity_name>
	<family>MAX7000S</family>
	<device>EPM7128SLC84-15</device>
	<timing_models>Final</timing_models>
	<met_timing_requirements>N/A</met_timing_requirements>
	<total_macrocells>10</total_macrocells>
	<total_pins>14</total_pins>
</compilation_summary>
<compile_id>B5C16CCC</compile_id>
</talkback>
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