cnt10b.tan.talkback.xml

通过ADC0809对模拟信号进行采样

<!--
This XML file (created on Wed Apr 30 15:51:02 2008) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to license.txt.
-->
<talkback>
<ver>5.1</ver>
<schema>quartus_version_5.1_build_176.xsd</schema><license>
	<host_id>0015c563ebaf</host_id>
	<nic_id>001302a85905</nic_id>
	<cdrive_id>6c0f603a</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>5.1</version>
	<build>Build 176</build>
	<binary_type>32</binary_type>
	<module>quartus_tan.exe</module>
	<edition>Full Version</edition>
	<compilation_end_time>Wed Apr 30 15:51:03 2008</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>2</proc_count>
		<cpu_freq units="MHz">1596</cpu_freq>
	</cpu>
	<ram units="MB">503</ram>
</machine>
<top_file>D:/CNT10B/cnt10b</top_file>
<mep_data>
	<command_line>quartus_tan --read_settings_files=off --write_settings_files=off cnt10b -c cnt10b</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<messages>
	<warning>Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew</warning>
	<warning>Warning: Found pins functioning as undefined clocks and/or memory enables</warning>
	<warning>Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family</warning>
	<info>Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings</info>
	<info>Info: Elapsed time: 00:00:01</info>
	<info>Info: Processing ended: Wed Apr 30 15:51:02 2008</info>
	<info>Info: Longest tpd from source pin &quot;we&quot; to destination pin &quot;clkout&quot; is 15.000 ns</info>
	<info>Info: Total interconnect delay = 2.000 ns ( 13.33 % )</info>
</messages>
<clock_settings_summary>
	<row>
		<clock_node_name>we</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
	<row>
		<clock_node_name>clk</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
	<row>
		<clock_node_name>lock0</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
</clock_settings_summary>
<performance>
	<nonclk>
		<type>Worst-case tco</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>23.000 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case tpd</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>15.000 ns</actual>
	</nonclk>
	<clk>
		<name>lock0</name>
		<slack>N/A</slack>
		<required>None</required>
		<actual>76.92 MHz ( period = 13.000 ns )</actual>
	</clk>
	<clk>
		<name>clk</name>
		<slack>N/A</slack>
		<required>None</required>
		<actual>76.92 MHz ( period = 13.000 ns )</actual>
	</clk>
	<clk>
		<name>we</name>
		<slack>N/A</slack>
		<required>None</required>
		<actual>76.92 MHz ( period = 13.000 ns )</actual>
	</clk>
</performance>
<compile_id>D69C95A0</compile_id>
</talkback>