cnt10b.rpp.talkback.xml

通过ADC0809对模拟信号进行采样

		<setting>Level2</setting>
		<default_value>Level2</default_value>
	</row>
</analysis___synthesis_settings>
<assembler_settings>
	<row>
		<option>Use smart compilation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Generate Serial Vector Format File (.svf) for Target Device</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Generate a JEDEC STAPL Format File (.jam) for Target Device</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Generate an uncompressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Compression mode</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Clock source for configuration device</option>
		<setting>Internal</setting>
		<default_value>Internal</default_value>
	</row>
	<row>
		<option>Clock frequency of the configuration device</option>
		<setting units="MHz">10</setting>
		<default_value units="MHz">10</default_value>
	</row>
	<row>
		<option>Divide clock frequency by</option>
		<setting>1</setting>
		<default_value>1</default_value>
	</row>
	<row>
		<option>JTAG user code for target device</option>
		<setting>Ffff</setting>
		<default_value>Ffff</default_value>
	</row>
	<row>
		<option>Auto user code</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Security bit</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Configuration device auto user code</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Generate Tabular Text File (.ttf) For Target Device</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Generate Raw Binary File (.rbf) For Target Device</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Hexadecimal Output File start address</option>
		<setting>0</setting>
		<default_value>0</default_value>
	</row>
	<row>
		<option>Hexadecimal Output File count direction</option>
		<setting>Up</setting>
		<default_value>Up</default_value>
	</row>
</assembler_settings>
<clock_settings_summary>
	<row>
		<clock_node_name>we</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
	<row>
		<clock_node_name>clk</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
	<row>
		<clock_node_name>lock0</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
</clock_settings_summary>
<input_pins>
	<row>
		<name>clk</name>
		<pin__>52</pin__>
		<lab>5</lab>
		<combinational_fan_out>3</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<input_register>no</input_register>
		<i_o_standard>TTL</i_o_standard>
		<location_assigned_by>Fitter</location_assigned_by>
	</row>
	<row>
		<name>clr</name>
		<pin__>33</pin__>
		<lab>4</lab>
		<combinational_fan_out>9</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<input_register>no</input_register>
		<i_o_standard>TTL</i_o_standard>
		<location_assigned_by>Fitter</location_assigned_by>
	</row>
	<row>
		<name>lock0</name>
		<pin__>24</pin__>
		<lab>3</lab>
		<combinational_fan_out>3</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<input_register>no</input_register>
		<i_o_standard>TTL</i_o_standard>
		<location_assigned_by>Fitter</location_assigned_by>
	</row>
	<row>
		<name>we</name>
		<pin__>81</pin__>
		<lab>8</lab>
		<combinational_fan_out>5</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<input_register>no</input_register>
		<i_o_standard>TTL</i_o_standard>
		<location_assigned_by>Fitter</location_assigned_by>
	</row>
</input_pins>
<output_pins>
	<row>
		<name>clkout</name>
		<pin__>21</pin__>
		<lab>2</lab>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>TTL</i_o_standard>
		<location_assigned_by>Fitter</location_assigned_by>
		<load>Unspecified</load>
	</row>
	<row>
		<name>dout[0]</name>
		<pin__>22</pin__>
		<lab>2</lab>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>TTL</i_o_standard>
		<location_assigned_by>Fitter</location_assigned_by>
		<load>Unspecified</load>
	</row>
	<row>
		<name>dout[1]</name>
		<pin__>4</pin__>
		<lab>1</lab>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>TTL</i_o_standard>
		<location_assigned_by>Fitter</location_assigned_by>
		<load>Unspecified</load>
	</row>
	<row>
		<name>dout[2]</name>
		<pin__>5</pin__>
		<lab>1</lab>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>TTL</i_o_standard>
		<location_assigned_by>Fitter</location_assigned_by>
		<load>Unspecified</load>
	</row>
	<row>
		<name>dout[3]</name>
		<pin__>6</pin__>
		<lab>1</lab>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>TTL</i_o_standard>
		<location_assigned_by>Fitter</location_assigned_by>
		<load>Unspecified</load>
	</row>
	<row>
		<name>dout[4]</name>
		<pin__>8</pin__>
		<lab>1</lab>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>TTL</i_o_standard>
		<location_assigned_by>Fitter</location_assigned_by>
		<load>Unspecified</load>
	</row>
	<row>
		<name>dout[5]</name>
		<pin__>9</pin__>
		<lab>1</lab>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>TTL</i_o_standard>
		<location_assigned_by>Fitter</location_assigned_by>
		<load>Unspecified</load>
	</row>
	<row>
		<name>dout[6]</name>
		<pin__>10</pin__>
		<lab>1</lab>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>TTL</i_o_standard>
		<location_assigned_by>Fitter</location_assigned_by>
		<load>Unspecified</load>
	</row>
	<row>
		<name>dout[7]</name>
		<pin__>11</pin__>
		<lab>1</lab>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>TTL</i_o_standard>
		<location_assigned_by>Fitter</location_assigned_by>
		<load>Unspecified</load>
	</row>
	<row>
		<name>dout[8]</name>
		<pin__>12</pin__>
		<lab>1</lab>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>TTL</i_o_standard>
		<location_assigned_by>Fitter</location_assigned_by>
		<load>Unspecified</load>
	</row>
</output_pins>
</talkback>