📄 adcint.map.rpt
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Analysis & Synthesis report for adcint
Wed Apr 30 15:35:32 2008
Version 5.1 Build 176 10/26/2005 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. State Machine - |adcint|current_state
8. Analysis & Synthesis Equations
9. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-----------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Apr 30 15:35:32 2008 ;
; Quartus II Version ; 5.1 Build 176 10/26/2005 SJ Web Edition ;
; Revision Name ; adcint ;
; Top-level Entity Name ; adcint ;
; Family ; MAX7000S ;
; Total macrocells ; 15 ;
; Total pins ; 23 ;
+-----------------------------+-----------------------------------------+
+--------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------+-----------------+---------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------+-----------------+---------------+
; Device ; EPM7128SLC84-15 ; ;
; Top-level entity name ; adcint ; adcint ;
; Family name ; MAX7000S ; Stratix ;
; Use smart compilation ; Off ; Off ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Auto ; Auto ;
; Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Off ; Off ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- MAX 7000B/7000AE/3000A/7000S/7000A ; Speed ; Speed ;
; Allow XOR Gate Usage ; On ; On ;
; Auto Logic Cell Insertion ; On ; On ;
; Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A ; 4 ; 4 ;
; Auto Parallel Expanders ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Maximum Fan-in Per Macrocell -- MAX 7000B/7000AE/3000A/7000S/7000A ; 100 ; 100 ;
; Ignore translate_off and translate_on Synthesis Directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; HDL message level ; Level2 ; Level2 ;
+----------------------------------------------------------------------+-----------------+---------------+
+-----------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+-----------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------+------------------------------+
; adcint.vhd ; yes ; Other ; D:/adcint/adcint.vhd ;
+----------------------------------+-----------------+-----------+------------------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource ; Usage ;
+----------------------+----------------------+
; Logic cells ; 15 ;
; Total registers ; 11 ;
; I/O pins ; 23 ;
; Maximum fan-out node ; current_state~9 ;
; Maximum fan-out ; 11 ;
; Total fan-out ; 46 ;
; Average fan-out ; 1.21 ;
+----------------------+----------------------+
+----------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+------------+------+---------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------+------------+------+---------------------+
; |adcint ; 15 ; 23 ; |adcint ;
+----------------------------+------------+------+---------------------+
+-------------------------------------------------------------------------+
; State Machine - |adcint|current_state ;
+-------------------+-----------------+-----------------+-----------------+
; Name ; current_state~9 ; current_state~8 ; current_state~7 ;
+-------------------+-----------------+-----------------+-----------------+
; current_state.st0 ; 0 ; 0 ; 0 ;
; current_state.st1 ; 0 ; 0 ; 1 ;
; current_state.st2 ; 0 ; 1 ; 0 ;
; current_state.st3 ; 0 ; 1 ; 1 ;
; current_state.st4 ; 1 ; 0 ; 0 ;
+-------------------+-----------------+-----------------+-----------------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/adcint/adcint.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition
Info: Processing started: Wed Apr 30 15:35:31 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adcint -c adcint
Warning: Using design file adcint.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: adcint-behav
Info: Found entity 1: adcint
Info: Elaborating entity "adcint" for the top level hierarchy
Info (10425): VHDL Case Statement information at adcint.vhd(34): OTHERS choice is never selected
Info: State machine "|adcint|current_state" contains 5 states
Info: Selected Auto state machine encoding method for state machine "|adcint|current_state"
Info: Encoding result for state machine "|adcint|current_state"
Info: Completed encoding using 3 state bits
Info: Encoded state bit "current_state~9"
Info: Encoded state bit "current_state~8"
Info: Encoded state bit "current_state~7"
Info: State "|adcint|current_state.st0" uses code string "000"
Info: State "|adcint|current_state.st1" uses code string "001"
Info: State "|adcint|current_state.st2" uses code string "010"
Info: State "|adcint|current_state.st3" uses code string "011"
Info: State "|adcint|current_state.st4" uses code string "100"
Warning: Output pins are stuck at VCC or GND
Warning: Pin "adda" stuck at VCC
Info: Promoted pin-driven signal(s) to global signal
Info: Promoted clock signal driven by pin "clk" to global clock signal
Info: Implemented 38 device resources after synthesis - the final resource count might be different
Info: Implemented 10 input pins
Info: Implemented 13 output pins
Info: Implemented 15 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
Info: Processing ended: Wed Apr 30 15:35:32 2008
Info: Elapsed time: 00:00:01
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