adcint.map.qmsg

通过ADC0809对模拟信号进行采样

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Web Edition " "Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 30 15:35:31 2008 " "Info: Processing started: Wed Apr 30 15:35:31 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off adcint -c adcint " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adcint -c adcint" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "adcint.vhd 2 1 " "Warning: Using design file adcint.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 adcint-behav " "Info: Found design unit 1: adcint-behav" {  } { { "adcint.vhd" "" { Text "D:/adcint/adcint.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 adcint " "Info: Found entity 1: adcint" {  } { { "adcint.vhd" "" { Text "D:/adcint/adcint.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "adcint " "Info: Elaborating entity \"adcint\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "adcint.vhd(34) " "Info (10425): VHDL Case Statement information at adcint.vhd(34): OTHERS choice is never selected" {  } { { "adcint.vhd" "" { Text "D:/adcint/adcint.vhd" 34 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|adcint\|current_state 5 " "Info: State machine \"\|adcint\|current_state\" contains 5 states" {  } { { "adcint.vhd" "" { Text "D:/adcint/adcint.vhd" 12 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|adcint\|current_state " "Info: Selected Auto state machine encoding method for state machine \"\|adcint\|current_state\"" {  } { { "adcint.vhd" "" { Text "D:/adcint/adcint.vhd" 12 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|adcint\|current_state " "Info: Encoding result for state machine \"\|adcint\|current_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "3 " "Info: Completed encoding using 3 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "current_state~9 " "Info: Encoded state bit \"current_state~9\"" {  } { { "adcint.vhd" "" { Text "D:/adcint/adcint.vhd" 12 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "current_state~8 " "Info: Encoded state bit \"current_state~8\"" {  } { { "adcint.vhd" "" { Text "D:/adcint/adcint.vhd" 12 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "current_state~7 " "Info: Encoded state bit \"current_state~7\"" {  } { { "adcint.vhd" "" { Text "D:/adcint/adcint.vhd" 12 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|adcint\|current_state.st0 000 " "Info: State \"\|adcint\|current_state.st0\" uses code string \"000\"" {  } { { "adcint.vhd" "" { Text "D:/adcint/adcint.vhd" 39 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|adcint\|current_state.st1 001 " "Info: State \"\|adcint\|current_state.st1\" uses code string \"001\"" {  } { { "adcint.vhd" "" { Text "D:/adcint/adcint.vhd" 39 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|adcint\|current_state.st2 010 " "Info: State \"\|adcint\|current_state.st2\" uses code string \"010\"" {  } { { "adcint.vhd" "" { Text "D:/adcint/adcint.vhd" 39 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|adcint\|current_state.st3 011 " "Info: State \"\|adcint\|current_state.st3\" uses code string \"011\"" {  } { { "adcint.vhd" "" { Text "D:/adcint/adcint.vhd" 39 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|adcint\|current_state.st4 100 " "Info: State \"\|adcint\|current_state.st4\" uses code string \"100\"" {  } { { "adcint.vhd" "" { Text "D:/adcint/adcint.vhd" 39 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "adcint.vhd" "" { Text "D:/adcint/adcint.vhd" 12 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "adda VCC " "Warning: Pin \"adda\" stuck at VCC" {  } { { "adcint.vhd" "" { Text "D:/adcint/adcint.vhd" 6 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0 0 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0}  } {  } 0 0 "Promoted pin-driven signal(s) to global signal" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "38 " "Info: Implemented 38 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "10 " "Info: Implemented 10 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "13 " "Info: Implemented 13 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_MCELLS" "15 " "Info: Implemented 15 macrocells" {  } {  } 0 0 "Implemented %1!d! macrocells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 30 15:35:32 2008 " "Info: Processing ended: Wed Apr 30 15:35:32 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}