adcint.tan.rpt

通过ADC0809对模拟信号进行采样

+--------------------------------------------------------------------------+
; tco                                                                      ;
+-------+--------------+------------+-----------------+-------+------------+
; Slack ; Required tco ; Actual tco ; From            ; To    ; From Clock ;
+-------+--------------+------------+-----------------+-------+------------+
; N/A   ; None         ; 17.000 ns  ; current_state~7 ; oe    ; clk        ;
; N/A   ; None         ; 17.000 ns  ; current_state~8 ; oe    ; clk        ;
; N/A   ; None         ; 17.000 ns  ; current_state~9 ; oe    ; clk        ;
; N/A   ; None         ; 17.000 ns  ; current_state~7 ; ale   ; clk        ;
; N/A   ; None         ; 17.000 ns  ; current_state~8 ; ale   ; clk        ;
; N/A   ; None         ; 17.000 ns  ; regl[7]         ; q[7]  ; clk        ;
; N/A   ; None         ; 17.000 ns  ; regl[6]         ; q[6]  ; clk        ;
; N/A   ; None         ; 17.000 ns  ; regl[5]         ; q[5]  ; clk        ;
; N/A   ; None         ; 17.000 ns  ; regl[4]         ; q[4]  ; clk        ;
; N/A   ; None         ; 17.000 ns  ; regl[3]         ; q[3]  ; clk        ;
; N/A   ; None         ; 17.000 ns  ; regl[2]         ; q[2]  ; clk        ;
; N/A   ; None         ; 17.000 ns  ; regl[1]         ; q[1]  ; clk        ;
; N/A   ; None         ; 17.000 ns  ; regl[0]         ; q[0]  ; clk        ;
; N/A   ; None         ; 17.000 ns  ; current_state~7 ; start ; clk        ;
; N/A   ; None         ; 17.000 ns  ; current_state~8 ; start ; clk        ;
; N/A   ; None         ; 8.000 ns   ; current_state~9 ; lock0 ; clk        ;
+-------+--------------+------------+-----------------+-------+------------+


+-----------------------------------------------------------------------------+
; th                                                                          ;
+---------------+-------------+-----------+------+-----------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To              ; To Clock ;
+---------------+-------------+-----------+------+-----------------+----------+
; N/A           ; None        ; 6.000 ns  ; d[0] ; regl[0]         ; clk      ;
; N/A           ; None        ; 6.000 ns  ; d[1] ; regl[1]         ; clk      ;
; N/A           ; None        ; 6.000 ns  ; d[2] ; regl[2]         ; clk      ;
; N/A           ; None        ; 6.000 ns  ; d[3] ; regl[3]         ; clk      ;
; N/A           ; None        ; 6.000 ns  ; d[4] ; regl[4]         ; clk      ;
; N/A           ; None        ; 6.000 ns  ; d[5] ; regl[5]         ; clk      ;
; N/A           ; None        ; 6.000 ns  ; d[6] ; regl[6]         ; clk      ;
; N/A           ; None        ; 6.000 ns  ; d[7] ; regl[7]         ; clk      ;
; N/A           ; None        ; -3.000 ns ; eoc  ; current_state~7 ; clk      ;
+---------------+-------------+-----------+------+-----------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition
    Info: Processing started: Wed Apr 30 15:35:38 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off adcint -c adcint
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "current_state~9" as buffer
Info: Clock "clk" has Internal fmax of 76.92 MHz between source register "current_state~7" and destination register "current_state~9" (period= 13.0 ns)
    Info: + Longest register to register delay is 8.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 7; REG Node = 'current_state~7'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC3; Fanout = 11; REG Node = 'current_state~9'
        Info: Total cell delay = 6.000 ns ( 75.00 % )
        Info: Total interconnect delay = 2.000 ns ( 25.00 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 3; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 11; REG Node = 'current_state~9'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
        Info: - Longest clock path from clock "clk" to source register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 3; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC1; Fanout = 7; REG Node = 'current_state~7'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Info: tsu for register "current_state~7" (data pin = "eoc", clock pin = "clk") is 11.000 ns
    Info: + Longest pin to register delay is 10.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_81; Fanout = 1; PIN Node = 'eoc'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC1; Fanout = 7; REG Node = 'current_state~7'
        Info: Total cell delay = 8.000 ns ( 80.00 % )
        Info: Total interconnect delay = 2.000 ns ( 20.00 % )
    Info: + Micro setup delay of destination is 4.000 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 3; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC1; Fanout = 7; REG Node = 'current_state~7'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: tco from clock "clk" to destination pin "oe" through register "current_state~7" is 17.000 ns
    Info: + Longest clock path from clock "clk" to source register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 3; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC1; Fanout = 7; REG Node = 'current_state~7'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Longest register to pin delay is 13.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 7; REG Node = 'current_state~7'
        Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC6; Fanout = 1; COMB Node = 'oe~6'
        Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_10; Fanout = 0; PIN Node = 'oe'
        Info: Total cell delay = 11.000 ns ( 84.62 % )
        Info: Total interconnect delay = 2.000 ns ( 15.38 % )
Info: th for register "regl[0]" (data pin = "d[0]", clock pin = "clk") is 6.000 ns
    Info: + Longest clock path from clock "clk" to destination register is 12.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 3; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC3; Fanout = 11; REG Node = 'current_state~9'
        Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC11; Fanout = 1; REG Node = 'regl[0]'
        Info: Total cell delay = 10.000 ns ( 83.33 % )
        Info: Total interconnect delay = 2.000 ns ( 16.67 % )
    Info: + Micro hold delay of destination is 4.000 ns
    Info: - Shortest pin to register delay is 10.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_34; Fanout = 1; PIN Node = 'd[0]'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC11; Fanout = 1; REG Node = 'regl[0]'
        Info: Total cell delay = 8.000 ns ( 80.00 % )
        Info: Total interconnect delay = 2.000 ns ( 20.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Processing ended: Wed Apr 30 15:35:38 2008
    Info: Elapsed time: 00:00:01