adcint.fit.eqn

通过ADC0809对模拟信号进行采样

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--A1L4 is current_state.st1~24 at LC13
A1L4_p1_out = A1L6Q & !A1L7Q;
A1L4_or_out = A1L4_p1_out;
A1L4 = A1L4_or_out;


--A1L7Q is current_state~8 at LC2
A1L7Q_or_out = !A1L6Q;
A1L7Q_reg_input = !A1L7Q_or_out;
A1L7Q = TFFE(A1L7Q_reg_input, GLOBAL(clk), , , );


--A1L8Q is current_state~9 at LC3
A1L8Q_p1_out = A1L6Q & A1L7Q;
A1L8Q_or_out = A1L8Q_p1_out;
A1L8Q_reg_input = A1L8Q_or_out;
A1L8Q = DFFE(A1L8Q_reg_input, GLOBAL(clk), , , );


--regl[7] is regl[7] at LC17
regl[7]_or_out = d[7];
regl[7]_reg_input = regl[7]_or_out;
regl[7] = DFFE(regl[7]_reg_input, A1L8Q, , , );


--regl[6] is regl[6] at LC19
regl[6]_or_out = d[6];
regl[6]_reg_input = regl[6]_or_out;
regl[6] = DFFE(regl[6]_reg_input, A1L8Q, , , );


--regl[5] is regl[5] at LC21
regl[5]_or_out = d[5];
regl[5]_reg_input = regl[5]_or_out;
regl[5] = DFFE(regl[5]_reg_input, A1L8Q, , , );


--regl[4] is regl[4] at LC25
regl[4]_or_out = d[4];
regl[4]_reg_input = regl[4]_or_out;
regl[4] = DFFE(regl[4]_reg_input, A1L8Q, , , );


--regl[3] is regl[3] at LC24
regl[3]_or_out = d[3];
regl[3]_reg_input = regl[3]_or_out;
regl[3] = DFFE(regl[3]_reg_input, A1L8Q, , , );


--regl[2] is regl[2] at LC16
regl[2]_or_out = d[2];
regl[2]_reg_input = regl[2]_or_out;
regl[2] = DFFE(regl[2]_reg_input, A1L8Q, , , );


--regl[1] is regl[1] at LC14
regl[1]_or_out = d[1];
regl[1]_reg_input = regl[1]_or_out;
regl[1] = DFFE(regl[1]_reg_input, A1L8Q, , , );


--regl[0] is regl[0] at LC11
regl[0]_or_out = d[0];
regl[0]_reg_input = regl[0]_or_out;
regl[0] = DFFE(regl[0]_reg_input, A1L8Q, , , );


--A1L6Q is current_state~7 at LC1
A1L6Q_p1_out = !A1L6Q & !A1L7Q & !A1L8Q;
A1L6Q_p2_out = !A1L6Q & A1L7Q & eoc;
A1L6Q_or_out = A1L6Q_p1_out # A1L6Q_p2_out;
A1L6Q_reg_input = A1L6Q_or_out;
A1L6Q = DFFE(A1L6Q_reg_input, GLOBAL(clk), , , );


--A1L5 is current_state.st1~26 at LC8
A1L5_p1_out = A1L6Q & !A1L7Q;
A1L5_or_out = A1L5_p1_out;
A1L5 = A1L5_or_out;


--A1L21 is oe~6 at LC6
A1L21_p1_out = A1L6Q & A1L7Q;
A1L21_or_out = A1L21_p1_out # A1L8Q;
A1L21 = A1L21_or_out;


--~VCC~0 is ~VCC~0 at LC5
~VCC~0_or_out = GND;
~VCC~0 = !(~VCC~0_or_out);


--d[0] is d[0] at PIN_34
--operation mode is input

d[0] = INPUT();


--d[1] is d[1] at PIN_52
--operation mode is input

d[1] = INPUT();


--d[2] is d[2] at PIN_70
--operation mode is input

d[2] = INPUT();


--d[3] is d[3] at PIN_15
--operation mode is input

d[3] = INPUT();


--d[4] is d[4] at PIN_61
--operation mode is input

d[4] = INPUT();


--d[5] is d[5] at PIN_80
--operation mode is input

d[5] = INPUT();


--d[6] is d[6] at PIN_24
--operation mode is input

d[6] = INPUT();


--d[7] is d[7] at PIN_33
--operation mode is input

d[7] = INPUT();


--clk is clk at PIN_83
--operation mode is input

clk = INPUT();


--eoc is eoc at PIN_81
--operation mode is input

eoc = INPUT();


--adda is adda at PIN_11
--operation mode is output

adda = OUTPUT(~VCC~0);


--start is start at PIN_6
--operation mode is output

start = OUTPUT(A1L4);


--lock0 is lock0 at PIN_12
--operation mode is output

lock0 = OUTPUT(A1L8Q);


--q[0] is q[0] at PIN_8
--operation mode is output

q[0] = OUTPUT(regl[0]);


--q[1] is q[1] at PIN_5
--operation mode is output

q[1] = OUTPUT(regl[1]);


--q[2] is q[2] at PIN_4
--operation mode is output

q[2] = OUTPUT(regl[2]);


--q[3] is q[3] at PIN_18
--operation mode is output

q[3] = OUTPUT(regl[3]);


--q[4] is q[4] at PIN_17
--operation mode is output

q[4] = OUTPUT(regl[4]);


--q[5] is q[5] at PIN_20
--operation mode is output

q[5] = OUTPUT(regl[5]);


--q[6] is q[6] at PIN_21
--operation mode is output

q[6] = OUTPUT(regl[6]);


--q[7] is q[7] at PIN_22
--operation mode is output

q[7] = OUTPUT(regl[7]);


--ale is ale at PIN_9
--operation mode is output

ale = OUTPUT(A1L5);


--oe is oe at PIN_10
--operation mode is output

oe = OUTPUT(A1L21);