📄 adcint.fit.rpt
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Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
+----------------------------------------------------------------------+
; Fitter Resource Utilization by Entity ;
+----------------------------+------------+------+---------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------+------------+------+---------------------+
; |adcint ; 15 ; 27 ; |adcint ;
+----------------------------+------------+------+---------------------+
+-------------------------------------------------------------------------------------------------+
; Control Signals ;
+-----------------+----------+---------+-------+--------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+-----------------+----------+---------+-------+--------+----------------------+------------------+
; clk ; PIN_83 ; 3 ; Clock ; yes ; On ; -- ;
; current_state~9 ; LC3 ; 11 ; Clock ; no ; -- ; -- ;
+-----------------+----------+---------+-------+--------+----------------------+------------------+
+---------------------------------------------------------------------+
; Global & Other Fast Signals ;
+------+----------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+------+----------+---------+----------------------+------------------+
; clk ; PIN_83 ; 3 ; On ; -- ;
+------+----------+---------+----------------------+------------------+
+---------------------------------+
; Non-Global High Fan-Out Signals ;
+----------------------+----------+
; Name ; Fan-Out ;
+----------------------+----------+
; current_state~9 ; 11 ;
; current_state~7 ; 6 ;
; current_state~8 ; 5 ;
; eoc ; 1 ;
; d[7] ; 1 ;
; d[6] ; 1 ;
; d[5] ; 1 ;
; d[4] ; 1 ;
; d[3] ; 1 ;
; d[2] ; 1 ;
; d[1] ; 1 ;
; d[0] ; 1 ;
; ~VCC~0 ; 1 ;
; oe~6 ; 1 ;
; current_state.st1~26 ; 1 ;
; regl[0] ; 1 ;
; regl[1] ; 1 ;
; regl[2] ; 1 ;
; regl[3] ; 1 ;
; regl[4] ; 1 ;
; regl[5] ; 1 ;
; regl[6] ; 1 ;
; regl[7] ; 1 ;
; current_state.st1~24 ; 1 ;
+----------------------+----------+
+-----------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+------------------+
; Output enables ; 0 / 6 ( 0 % ) ;
; PIA buffers ; 13 / 288 ( 5 % ) ;
; PIAs ; 13 / 288 ( 5 % ) ;
+----------------------------+------------------+
+----------------------------------------------------------------------------+
; LAB External Interconnect ;
+----------------------------------------------+-----------------------------+
; LAB External Interconnects (Average = 1.63) ; Number of LABs (Total = 2) ;
+----------------------------------------------+-----------------------------+
; 0 ; 6 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 1 ;
+----------------------------------------------+-----------------------------+
+----------------------------------------------------------------------+
; LAB Macrocells ;
+----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 1.88) ; Number of LABs (Total = 2) ;
+----------------------------------------+-----------------------------+
; 0 ; 6 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 1 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 1 ;
+----------------------------------------+-----------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+-------------------------------------------------------------+------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+-------------------------------------------------------------+------------------------------------------------------------------------------------------------------+
; A ; LC13 ; current_state~7, current_state~8 ; start ;
; A ; LC2 ; clk, current_state~7 ; current_state.st1~24, current_state~9, current_state~7, current_state.st1~26, oe~6 ;
; A ; LC3 ; clk, current_state~7, current_state~8 ; regl[7], regl[6], regl[5], regl[4], regl[3], regl[2], regl[1], regl[0], lock0, current_state~7, oe~6 ;
; A ; LC16 ; d[2], current_state~9 ; q[2] ;
; A ; LC14 ; d[1], current_state~9 ; q[1] ;
; A ; LC11 ; d[0], current_state~9 ; q[0] ;
; A ; LC1 ; clk, current_state~7, current_state~8, current_state~9, eoc ; current_state.st1~24, current_state~8, current_state~9, current_state~7, current_state.st1~26, oe~6 ;
; A ; LC8 ; current_state~7, current_state~8 ; ale ;
; A ; LC6 ; current_state~7, current_state~8, current_state~9 ; oe ;
; A ; LC5 ; ; adda ;
; B ; LC17 ; d[7], current_state~9 ; q[7] ;
; B ; LC19 ; d[6], current_state~9 ; q[6] ;
; B ; LC21 ; d[5], current_state~9 ; q[5] ;
; B ; LC25 ; d[4], current_state~9 ; q[4] ;
; B ; LC24 ; d[3], current_state~9 ; q[3] ;
+-----+------------+-------------------------------------------------------------+------------------------------------------------------------------------------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition
Info: Processing started: Wed Apr 30 15:35:34 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off adcint -c adcint
Info: Selected device EPM7128SLC84-15 for design "adcint"
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Wed Apr 30 15:35:34 2008
Info: Elapsed time: 00:00:01
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