shujucaiji.map.eqn

通过ADC0809对模拟信号进行采样

--RAM Block Operation Mode: Single Port
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
G1_q_a[1]_PORT_A_data_in = B1_regl[1];
G1_q_a[1]_PORT_A_data_in_reg = DFFE(G1_q_a[1]_PORT_A_data_in, G1_q_a[1]_clock_0, , , );
G1_q_a[1]_PORT_A_address = BUS(C1_cqi[0], C1_cqi[1], C1_cqi[2], C1_cqi[3], C1_cqi[4], C1_cqi[5], C1_cqi[6], C1_cqi[7], C1_cqi[8]);
G1_q_a[1]_PORT_A_address_reg = DFFE(G1_q_a[1]_PORT_A_address, G1_q_a[1]_clock_0, , , );
G1_q_a[1]_PORT_B_address = BUS(C1_cqi[0], C1_cqi[1], C1_cqi[2], C1_cqi[3], C1_cqi[4], C1_cqi[5], C1_cqi[6], C1_cqi[7], C1_cqi[8]);
G1_q_a[1]_PORT_B_address_reg = DFFE(G1_q_a[1]_PORT_B_address, G1_q_a[1]_clock_0, , , );
G1_q_a[1]_PORT_A_write_enable = wren;
G1_q_a[1]_PORT_A_write_enable_reg = DFFE(G1_q_a[1]_PORT_A_write_enable, G1_q_a[1]_clock_0, , , );
G1_q_a[1]_clock_0 = C1L1;
G1_q_a[1]_PORT_A_data_out = MEMORY(G1_q_a[1]_PORT_A_data_in_reg, , G1_q_a[1]_PORT_A_address_reg, G1_q_a[1]_PORT_B_address_reg, G1_q_a[1]_PORT_A_write_enable_reg, , , , G1_q_a[1]_clock_0, , , , , );
G1_q_a[1] = G1_q_a[1]_PORT_A_data_out[0];


--G1_q_a[0] is ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[0]
--RAM Block Operation Mode: Single Port
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
G1_q_a[0]_PORT_A_data_in = B1_regl[0];
G1_q_a[0]_PORT_A_data_in_reg = DFFE(G1_q_a[0]_PORT_A_data_in, G1_q_a[0]_clock_0, , , );
G1_q_a[0]_PORT_A_address = BUS(C1_cqi[0], C1_cqi[1], C1_cqi[2], C1_cqi[3], C1_cqi[4], C1_cqi[5], C1_cqi[6], C1_cqi[7], C1_cqi[8]);
G1_q_a[0]_PORT_A_address_reg = DFFE(G1_q_a[0]_PORT_A_address, G1_q_a[0]_clock_0, , , );
G1_q_a[0]_PORT_B_address = BUS(C1_cqi[0], C1_cqi[1], C1_cqi[2], C1_cqi[3], C1_cqi[4], C1_cqi[5], C1_cqi[6], C1_cqi[7], C1_cqi[8]);
G1_q_a[0]_PORT_B_address_reg = DFFE(G1_q_a[0]_PORT_B_address, G1_q_a[0]_clock_0, , , );
G1_q_a[0]_PORT_A_write_enable = wren;
G1_q_a[0]_PORT_A_write_enable_reg = DFFE(G1_q_a[0]_PORT_A_write_enable, G1_q_a[0]_clock_0, , , );
G1_q_a[0]_clock_0 = C1L1;
G1_q_a[0]_PORT_A_data_out = MEMORY(G1_q_a[0]_PORT_A_data_in_reg, , G1_q_a[0]_PORT_A_address_reg, G1_q_a[0]_PORT_B_address_reg, G1_q_a[0]_PORT_A_write_enable_reg, , , , G1_q_a[0]_clock_0, , , , , );
G1_q_a[0] = G1_q_a[0]_PORT_A_data_out[0];


--B1_current_state.st0 is adcint:inst|current_state.st0
--operation mode is normal

B1_current_state.st0_lut_out = !B1_current_state.st4;
B1_current_state.st0 = DFFEAS(B1_current_state.st0_lut_out, clk, VCC, , , , , , );


--B1_current_state.st2 is adcint:inst|current_state.st2
--operation mode is normal

B1_current_state.st2_lut_out = B1_current_state.st1 # B1_current_state.st2 & (!eoc);
B1_current_state.st2 = DFFEAS(B1_current_state.st2_lut_out, clk, VCC, , , , , , );


--B1_regl[7] is adcint:inst|regl[7]
--operation mode is normal

B1_regl[7]_lut_out = d[7];
B1_regl[7] = DFFEAS(B1_regl[7]_lut_out, B1_current_state.st4, VCC, , , , , , );


--B1_regl[6] is adcint:inst|regl[6]
--operation mode is normal

B1_regl[6]_lut_out = d[6];
B1_regl[6] = DFFEAS(B1_regl[6]_lut_out, B1_current_state.st4, VCC, , , , , , );


--B1_regl[5] is adcint:inst|regl[5]
--operation mode is normal

B1_regl[5]_lut_out = d[5];
B1_regl[5] = DFFEAS(B1_regl[5]_lut_out, B1_current_state.st4, VCC, , , , , , );


--B1_regl[4] is adcint:inst|regl[4]
--operation mode is normal

B1_regl[4]_lut_out = d[4];
B1_regl[4] = DFFEAS(B1_regl[4]_lut_out, B1_current_state.st4, VCC, , , , , , );


--B1_regl[3] is adcint:inst|regl[3]
--operation mode is normal

B1_regl[3]_lut_out = d[3];
B1_regl[3] = DFFEAS(B1_regl[3]_lut_out, B1_current_state.st4, VCC, , , , , , );


--B1_regl[2] is adcint:inst|regl[2]
--operation mode is normal

B1_regl[2]_lut_out = d[2];
B1_regl[2] = DFFEAS(B1_regl[2]_lut_out, B1_current_state.st4, VCC, , , , , , );


--B1_regl[1] is adcint:inst|regl[1]
--operation mode is normal

B1_regl[1]_lut_out = d[1];
B1_regl[1] = DFFEAS(B1_regl[1]_lut_out, B1_current_state.st4, VCC, , , , , , );


--B1_regl[0] is adcint:inst|regl[0]
--operation mode is normal

B1_regl[0]_lut_out = d[0];
B1_regl[0] = DFFEAS(B1_regl[0]_lut_out, B1_current_state.st4, VCC, , , , , , );


--clk is clk
--operation mode is input

clk = INPUT();


--wren is wren
--operation mode is input

wren = INPUT();


--eoc is eoc
--operation mode is input

eoc = INPUT();


--clr is clr
--operation mode is input

clr = INPUT();


--d[7] is d[7]
--operation mode is input

d[7] = INPUT();


--d[6] is d[6]
--operation mode is input

d[6] = INPUT();


--d[5] is d[5]
--operation mode is input

d[5] = INPUT();


--d[4] is d[4]
--operation mode is input

d[4] = INPUT();


--d[3] is d[3]
--operation mode is input

d[3] = INPUT();


--d[2] is d[2]
--operation mode is input

d[2] = INPUT();


--d[1] is d[1]
--operation mode is input

d[1] = INPUT();


--d[0] is d[0]
--operation mode is input

d[0] = INPUT();


--ale is ale
--operation mode is output

ale = OUTPUT(B1_current_state.st1);


--start is start
--operation mode is output

start = OUTPUT(B1_current_state.st1);


--oe is oe
--operation mode is output

oe = OUTPUT(B1_oe);


--adda is adda
--operation mode is output

adda = OUTPUT(VCC);


--lock0 is lock0
--operation mode is output

lock0 = OUTPUT(B1_current_state.st4);


--inclock is inclock
--operation mode is output

inclock = OUTPUT(C1L1);


--address[8] is address[8]
--operation mode is output

address[8] = OUTPUT(C1_cqi[8]);


--address[7] is address[7]
--operation mode is output

address[7] = OUTPUT(C1_cqi[7]);


--address[6] is address[6]
--operation mode is output

address[6] = OUTPUT(C1_cqi[6]);


--address[5] is address[5]
--operation mode is output

address[5] = OUTPUT(C1_cqi[5]);


--address[4] is address[4]
--operation mode is output

address[4] = OUTPUT(C1_cqi[4]);


--address[3] is address[3]
--operation mode is output

address[3] = OUTPUT(C1_cqi[3]);


--address[2] is address[2]
--operation mode is output

address[2] = OUTPUT(C1_cqi[2]);


--address[1] is address[1]
--operation mode is output

address[1] = OUTPUT(C1_cqi[1]);


--address[0] is address[0]
--operation mode is output

address[0] = OUTPUT(C1_cqi[0]);


--joc[7] is joc[7]
--operation mode is output

joc[7] = OUTPUT(J1_safe_q[7]);


--joc[6] is joc[6]
--operation mode is output

joc[6] = OUTPUT(J1_safe_q[6]);


--joc[5] is joc[5]
--operation mode is output

joc[5] = OUTPUT(J1_safe_q[5]);


--joc[4] is joc[4]
--operation mode is output

joc[4] = OUTPUT(J1_safe_q[4]);


--joc[3] is joc[3]
--operation mode is output

joc[3] = OUTPUT(J1_safe_q[3]);


--joc[2] is joc[2]
--operation mode is output

joc[2] = OUTPUT(J1_safe_q[2]);


--joc[1] is joc[1]
--operation mode is output

joc[1] = OUTPUT(J1_safe_q[1]);


--joc[0] is joc[0]
--operation mode is output

joc[0] = OUTPUT(J1_safe_q[0]);


--q[7] is q[7]
--operation mode is output

q[7] = OUTPUT(G1_q_a[7]);


--q[6] is q[6]
--operation mode is output

q[6] = OUTPUT(G1_q_a[6]);


--q[5] is q[5]
--operation mode is output

q[5] = OUTPUT(G1_q_a[5]);


--q[4] is q[4]
--operation mode is output

q[4] = OUTPUT(G1_q_a[4]);


--q[3] is q[3]
--operation mode is output

q[3] = OUTPUT(G1_q_a[3]);


--q[2] is q[2]
--operation mode is output

q[2] = OUTPUT(G1_q_a[2]);


--q[1] is q[1]
--operation mode is output

q[1] = OUTPUT(G1_q_a[1]);


--q[0] is q[0]
--operation mode is output

q[0] = OUTPUT(G1_q_a[0]);