shujucaiji.map.eqn

通过ADC0809对模拟信号进行采样

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--B1_current_state.st1 is adcint:inst|current_state.st1
--operation mode is normal

B1_current_state.st1_lut_out = !B1_current_state.st0;
B1_current_state.st1 = DFFEAS(B1_current_state.st1_lut_out, clk, VCC, , , , , , );


--B1_current_state.st3 is adcint:inst|current_state.st3
--operation mode is normal

B1_current_state.st3_lut_out = B1_current_state.st2 & eoc;
B1_current_state.st3 = DFFEAS(B1_current_state.st3_lut_out, clk, VCC, , , , , , );


--B1_current_state.st4 is adcint:inst|current_state.st4
--operation mode is normal

B1_current_state.st4_lut_out = B1_current_state.st3;
B1_current_state.st4 = DFFEAS(B1_current_state.st4_lut_out, clk, VCC, , , , , , );


--B1_oe is adcint:inst|oe
--operation mode is normal

B1_oe = B1_current_state.st3 # B1_current_state.st4;


--C1L1 is cnt10b:inst1|clkout~7
--operation mode is normal

C1L1 = wren & B1_current_state.st4 # !wren & (clk);


--C1_cqi[8] is cnt10b:inst1|cqi[8]
--operation mode is normal

C1_cqi[8]_carry_eqn = C1L18;
C1_cqi[8]_lut_out = C1_cqi[8] $ (!C1_cqi[8]_carry_eqn);
C1_cqi[8] = DFFEAS(C1_cqi[8]_lut_out, C1L1, !clr, , , , , , );


--C1_cqi[7] is cnt10b:inst1|cqi[7]
--operation mode is arithmetic

C1_cqi[7]_carry_eqn = C1L16;
C1_cqi[7]_lut_out = C1_cqi[7] $ (C1_cqi[7]_carry_eqn);
C1_cqi[7] = DFFEAS(C1_cqi[7]_lut_out, C1L1, !clr, , , , , , );

--C1L18 is cnt10b:inst1|cqi[7]~68
--operation mode is arithmetic

C1L18 = CARRY(!C1L16 # !C1_cqi[7]);


--C1_cqi[6] is cnt10b:inst1|cqi[6]
--operation mode is arithmetic

C1_cqi[6]_carry_eqn = C1L14;
C1_cqi[6]_lut_out = C1_cqi[6] $ (!C1_cqi[6]_carry_eqn);
C1_cqi[6] = DFFEAS(C1_cqi[6]_lut_out, C1L1, !clr, , , , , , );

--C1L16 is cnt10b:inst1|cqi[6]~72
--operation mode is arithmetic

C1L16 = CARRY(C1_cqi[6] & (!C1L14));


--C1_cqi[5] is cnt10b:inst1|cqi[5]
--operation mode is arithmetic

C1_cqi[5]_carry_eqn = C1L12;
C1_cqi[5]_lut_out = C1_cqi[5] $ (C1_cqi[5]_carry_eqn);
C1_cqi[5] = DFFEAS(C1_cqi[5]_lut_out, C1L1, !clr, , , , , , );

--C1L14 is cnt10b:inst1|cqi[5]~76
--operation mode is arithmetic

C1L14 = CARRY(!C1L12 # !C1_cqi[5]);


--C1_cqi[4] is cnt10b:inst1|cqi[4]
--operation mode is arithmetic

C1_cqi[4]_carry_eqn = C1L10;
C1_cqi[4]_lut_out = C1_cqi[4] $ (!C1_cqi[4]_carry_eqn);
C1_cqi[4] = DFFEAS(C1_cqi[4]_lut_out, C1L1, !clr, , , , , , );

--C1L12 is cnt10b:inst1|cqi[4]~80
--operation mode is arithmetic

C1L12 = CARRY(C1_cqi[4] & (!C1L10));


--C1_cqi[3] is cnt10b:inst1|cqi[3]
--operation mode is arithmetic

C1_cqi[3]_carry_eqn = C1L8;
C1_cqi[3]_lut_out = C1_cqi[3] $ (C1_cqi[3]_carry_eqn);
C1_cqi[3] = DFFEAS(C1_cqi[3]_lut_out, C1L1, !clr, , , , , , );

--C1L10 is cnt10b:inst1|cqi[3]~84
--operation mode is arithmetic

C1L10 = CARRY(!C1L8 # !C1_cqi[3]);


--C1_cqi[2] is cnt10b:inst1|cqi[2]
--operation mode is arithmetic

C1_cqi[2]_carry_eqn = C1L6;
C1_cqi[2]_lut_out = C1_cqi[2] $ (!C1_cqi[2]_carry_eqn);
C1_cqi[2] = DFFEAS(C1_cqi[2]_lut_out, C1L1, !clr, , , , , , );

--C1L8 is cnt10b:inst1|cqi[2]~88
--operation mode is arithmetic

C1L8 = CARRY(C1_cqi[2] & (!C1L6));


--C1_cqi[1] is cnt10b:inst1|cqi[1]
--operation mode is arithmetic

C1_cqi[1]_carry_eqn = C1L4;
C1_cqi[1]_lut_out = C1_cqi[1] $ (C1_cqi[1]_carry_eqn);
C1_cqi[1] = DFFEAS(C1_cqi[1]_lut_out, C1L1, !clr, , , , , , );

--C1L6 is cnt10b:inst1|cqi[1]~92
--operation mode is arithmetic

C1L6 = CARRY(!C1L4 # !C1_cqi[1]);


--C1_cqi[0] is cnt10b:inst1|cqi[0]
--operation mode is arithmetic

C1_cqi[0]_lut_out = !C1_cqi[0];
C1_cqi[0] = DFFEAS(C1_cqi[0]_lut_out, C1L1, !clr, , , , , , );

--C1L4 is cnt10b:inst1|cqi[0]~96
--operation mode is arithmetic

C1L4 = CARRY(C1_cqi[0]);


--J1_safe_q[7] is lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated|safe_q[7]
--operation mode is normal

J1_safe_q[7]_carry_eqn = J1L14;
J1_safe_q[7]_lut_out = J1_safe_q[7] $ (J1_safe_q[7]_carry_eqn);
J1_safe_q[7] = DFFEAS(J1_safe_q[7]_lut_out, clk, VCC, , !wren, , , , );


--J1_safe_q[6] is lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated|safe_q[6]
--operation mode is arithmetic

J1_safe_q[6]_carry_eqn = J1L12;
J1_safe_q[6]_lut_out = J1_safe_q[6] $ (!J1_safe_q[6]_carry_eqn);
J1_safe_q[6] = DFFEAS(J1_safe_q[6]_lut_out, clk, VCC, , !wren, , , , );

--J1L14 is lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated|counter_cella6~COUT
--operation mode is arithmetic

J1L14 = CARRY(J1_safe_q[6] & (!J1L12));


--J1_safe_q[5] is lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated|safe_q[5]
--operation mode is arithmetic

J1_safe_q[5]_carry_eqn = J1L10;
J1_safe_q[5]_lut_out = J1_safe_q[5] $ (J1_safe_q[5]_carry_eqn);
J1_safe_q[5] = DFFEAS(J1_safe_q[5]_lut_out, clk, VCC, , !wren, , , , );

--J1L12 is lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated|counter_cella5~COUT
--operation mode is arithmetic

J1L12 = CARRY(!J1L10 # !J1_safe_q[5]);


--J1_safe_q[4] is lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated|safe_q[4]
--operation mode is arithmetic

J1_safe_q[4]_carry_eqn = J1L8;
J1_safe_q[4]_lut_out = J1_safe_q[4] $ (!J1_safe_q[4]_carry_eqn);
J1_safe_q[4] = DFFEAS(J1_safe_q[4]_lut_out, clk, VCC, , !wren, , , , );

--J1L10 is lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated|counter_cella4~COUT
--operation mode is arithmetic

J1L10 = CARRY(J1_safe_q[4] & (!J1L8));


--J1_safe_q[3] is lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated|safe_q[3]
--operation mode is arithmetic

J1_safe_q[3]_carry_eqn = J1L6;
J1_safe_q[3]_lut_out = J1_safe_q[3] $ (J1_safe_q[3]_carry_eqn);
J1_safe_q[3] = DFFEAS(J1_safe_q[3]_lut_out, clk, VCC, , !wren, , , , );

--J1L8 is lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated|counter_cella3~COUT
--operation mode is arithmetic

J1L8 = CARRY(!J1L6 # !J1_safe_q[3]);


--J1_safe_q[2] is lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated|safe_q[2]
--operation mode is arithmetic

J1_safe_q[2]_carry_eqn = J1L4;
J1_safe_q[2]_lut_out = J1_safe_q[2] $ (!J1_safe_q[2]_carry_eqn);
J1_safe_q[2] = DFFEAS(J1_safe_q[2]_lut_out, clk, VCC, , !wren, , , , );

--J1L6 is lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated|counter_cella2~COUT
--operation mode is arithmetic

J1L6 = CARRY(J1_safe_q[2] & (!J1L4));


--J1_safe_q[1] is lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated|safe_q[1]
--operation mode is arithmetic

J1_safe_q[1]_carry_eqn = J1L2;
J1_safe_q[1]_lut_out = J1_safe_q[1] $ (J1_safe_q[1]_carry_eqn);
J1_safe_q[1] = DFFEAS(J1_safe_q[1]_lut_out, clk, VCC, , !wren, , , , );

--J1L4 is lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated|counter_cella1~COUT
--operation mode is arithmetic

J1L4 = CARRY(!J1L2 # !J1_safe_q[1]);


--J1_safe_q[0] is lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated|safe_q[0]
--operation mode is arithmetic

J1_safe_q[0]_lut_out = !J1_safe_q[0];
J1_safe_q[0] = DFFEAS(J1_safe_q[0]_lut_out, clk, VCC, , !wren, , , , );

--J1L2 is lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated|counter_cella0~COUT
--operation mode is arithmetic

J1L2 = CARRY(J1_safe_q[0]);


--G1_q_a[7] is ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[7]
--RAM Block Operation Mode: Single Port
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
G1_q_a[7]_PORT_A_data_in = B1_regl[7];
G1_q_a[7]_PORT_A_data_in_reg = DFFE(G1_q_a[7]_PORT_A_data_in, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_PORT_A_address = BUS(C1_cqi[0], C1_cqi[1], C1_cqi[2], C1_cqi[3], C1_cqi[4], C1_cqi[5], C1_cqi[6], C1_cqi[7], C1_cqi[8]);
G1_q_a[7]_PORT_A_address_reg = DFFE(G1_q_a[7]_PORT_A_address, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_PORT_B_address = BUS(C1_cqi[0], C1_cqi[1], C1_cqi[2], C1_cqi[3], C1_cqi[4], C1_cqi[5], C1_cqi[6], C1_cqi[7], C1_cqi[8]);
G1_q_a[7]_PORT_B_address_reg = DFFE(G1_q_a[7]_PORT_B_address, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_PORT_A_write_enable = wren;
G1_q_a[7]_PORT_A_write_enable_reg = DFFE(G1_q_a[7]_PORT_A_write_enable, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_clock_0 = C1L1;
G1_q_a[7]_PORT_A_data_out = MEMORY(G1_q_a[7]_PORT_A_data_in_reg, , G1_q_a[7]_PORT_A_address_reg, G1_q_a[7]_PORT_B_address_reg, G1_q_a[7]_PORT_A_write_enable_reg, , , , G1_q_a[7]_clock_0, , , , , );
G1_q_a[7] = G1_q_a[7]_PORT_A_data_out[0];


--G1_q_a[6] is ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[6]
--RAM Block Operation Mode: Single Port
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
G1_q_a[6]_PORT_A_data_in = B1_regl[6];
G1_q_a[6]_PORT_A_data_in_reg = DFFE(G1_q_a[6]_PORT_A_data_in, G1_q_a[6]_clock_0, , , );
G1_q_a[6]_PORT_A_address = BUS(C1_cqi[0], C1_cqi[1], C1_cqi[2], C1_cqi[3], C1_cqi[4], C1_cqi[5], C1_cqi[6], C1_cqi[7], C1_cqi[8]);
G1_q_a[6]_PORT_A_address_reg = DFFE(G1_q_a[6]_PORT_A_address, G1_q_a[6]_clock_0, , , );
G1_q_a[6]_PORT_B_address = BUS(C1_cqi[0], C1_cqi[1], C1_cqi[2], C1_cqi[3], C1_cqi[4], C1_cqi[5], C1_cqi[6], C1_cqi[7], C1_cqi[8]);
G1_q_a[6]_PORT_B_address_reg = DFFE(G1_q_a[6]_PORT_B_address, G1_q_a[6]_clock_0, , , );
G1_q_a[6]_PORT_A_write_enable = wren;
G1_q_a[6]_PORT_A_write_enable_reg = DFFE(G1_q_a[6]_PORT_A_write_enable, G1_q_a[6]_clock_0, , , );
G1_q_a[6]_clock_0 = C1L1;
G1_q_a[6]_PORT_A_data_out = MEMORY(G1_q_a[6]_PORT_A_data_in_reg, , G1_q_a[6]_PORT_A_address_reg, G1_q_a[6]_PORT_B_address_reg, G1_q_a[6]_PORT_A_write_enable_reg, , , , G1_q_a[6]_clock_0, , , , , );
G1_q_a[6] = G1_q_a[6]_PORT_A_data_out[0];


--G1_q_a[5] is ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[5]
--RAM Block Operation Mode: Single Port
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
G1_q_a[5]_PORT_A_data_in = B1_regl[5];
G1_q_a[5]_PORT_A_data_in_reg = DFFE(G1_q_a[5]_PORT_A_data_in, G1_q_a[5]_clock_0, , , );
G1_q_a[5]_PORT_A_address = BUS(C1_cqi[0], C1_cqi[1], C1_cqi[2], C1_cqi[3], C1_cqi[4], C1_cqi[5], C1_cqi[6], C1_cqi[7], C1_cqi[8]);
G1_q_a[5]_PORT_A_address_reg = DFFE(G1_q_a[5]_PORT_A_address, G1_q_a[5]_clock_0, , , );
G1_q_a[5]_PORT_B_address = BUS(C1_cqi[0], C1_cqi[1], C1_cqi[2], C1_cqi[3], C1_cqi[4], C1_cqi[5], C1_cqi[6], C1_cqi[7], C1_cqi[8]);
G1_q_a[5]_PORT_B_address_reg = DFFE(G1_q_a[5]_PORT_B_address, G1_q_a[5]_clock_0, , , );
G1_q_a[5]_PORT_A_write_enable = wren;
G1_q_a[5]_PORT_A_write_enable_reg = DFFE(G1_q_a[5]_PORT_A_write_enable, G1_q_a[5]_clock_0, , , );
G1_q_a[5]_clock_0 = C1L1;
G1_q_a[5]_PORT_A_data_out = MEMORY(G1_q_a[5]_PORT_A_data_in_reg, , G1_q_a[5]_PORT_A_address_reg, G1_q_a[5]_PORT_B_address_reg, G1_q_a[5]_PORT_A_write_enable_reg, , , , G1_q_a[5]_clock_0, , , , , );
G1_q_a[5] = G1_q_a[5]_PORT_A_data_out[0];


--G1_q_a[4] is ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[4]
--RAM Block Operation Mode: Single Port
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
G1_q_a[4]_PORT_A_data_in = B1_regl[4];
G1_q_a[4]_PORT_A_data_in_reg = DFFE(G1_q_a[4]_PORT_A_data_in, G1_q_a[4]_clock_0, , , );
G1_q_a[4]_PORT_A_address = BUS(C1_cqi[0], C1_cqi[1], C1_cqi[2], C1_cqi[3], C1_cqi[4], C1_cqi[5], C1_cqi[6], C1_cqi[7], C1_cqi[8]);
G1_q_a[4]_PORT_A_address_reg = DFFE(G1_q_a[4]_PORT_A_address, G1_q_a[4]_clock_0, , , );
G1_q_a[4]_PORT_B_address = BUS(C1_cqi[0], C1_cqi[1], C1_cqi[2], C1_cqi[3], C1_cqi[4], C1_cqi[5], C1_cqi[6], C1_cqi[7], C1_cqi[8]);
G1_q_a[4]_PORT_B_address_reg = DFFE(G1_q_a[4]_PORT_B_address, G1_q_a[4]_clock_0, , , );
G1_q_a[4]_PORT_A_write_enable = wren;
G1_q_a[4]_PORT_A_write_enable_reg = DFFE(G1_q_a[4]_PORT_A_write_enable, G1_q_a[4]_clock_0, , , );
G1_q_a[4]_clock_0 = C1L1;
G1_q_a[4]_PORT_A_data_out = MEMORY(G1_q_a[4]_PORT_A_data_in_reg, , G1_q_a[4]_PORT_A_address_reg, G1_q_a[4]_PORT_B_address_reg, G1_q_a[4]_PORT_A_write_enable_reg, , , , G1_q_a[4]_clock_0, , , , , );
G1_q_a[4] = G1_q_a[4]_PORT_A_data_out[0];


--G1_q_a[3] is ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[3]
--RAM Block Operation Mode: Single Port
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
G1_q_a[3]_PORT_A_data_in = B1_regl[3];
G1_q_a[3]_PORT_A_data_in_reg = DFFE(G1_q_a[3]_PORT_A_data_in, G1_q_a[3]_clock_0, , , );
G1_q_a[3]_PORT_A_address = BUS(C1_cqi[0], C1_cqi[1], C1_cqi[2], C1_cqi[3], C1_cqi[4], C1_cqi[5], C1_cqi[6], C1_cqi[7], C1_cqi[8]);
G1_q_a[3]_PORT_A_address_reg = DFFE(G1_q_a[3]_PORT_A_address, G1_q_a[3]_clock_0, , , );
G1_q_a[3]_PORT_B_address = BUS(C1_cqi[0], C1_cqi[1], C1_cqi[2], C1_cqi[3], C1_cqi[4], C1_cqi[5], C1_cqi[6], C1_cqi[7], C1_cqi[8]);
G1_q_a[3]_PORT_B_address_reg = DFFE(G1_q_a[3]_PORT_B_address, G1_q_a[3]_clock_0, , , );
G1_q_a[3]_PORT_A_write_enable = wren;
G1_q_a[3]_PORT_A_write_enable_reg = DFFE(G1_q_a[3]_PORT_A_write_enable, G1_q_a[3]_clock_0, , , );
G1_q_a[3]_clock_0 = C1L1;
G1_q_a[3]_PORT_A_data_out = MEMORY(G1_q_a[3]_PORT_A_data_in_reg, , G1_q_a[3]_PORT_A_address_reg, G1_q_a[3]_PORT_B_address_reg, G1_q_a[3]_PORT_A_write_enable_reg, , , , G1_q_a[3]_clock_0, , , , , );
G1_q_a[3] = G1_q_a[3]_PORT_A_data_out[0];


--G1_q_a[2] is ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[2]
--RAM Block Operation Mode: Single Port
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
G1_q_a[2]_PORT_A_data_in = B1_regl[2];
G1_q_a[2]_PORT_A_data_in_reg = DFFE(G1_q_a[2]_PORT_A_data_in, G1_q_a[2]_clock_0, , , );
G1_q_a[2]_PORT_A_address = BUS(C1_cqi[0], C1_cqi[1], C1_cqi[2], C1_cqi[3], C1_cqi[4], C1_cqi[5], C1_cqi[6], C1_cqi[7], C1_cqi[8]);
G1_q_a[2]_PORT_A_address_reg = DFFE(G1_q_a[2]_PORT_A_address, G1_q_a[2]_clock_0, , , );
G1_q_a[2]_PORT_B_address = BUS(C1_cqi[0], C1_cqi[1], C1_cqi[2], C1_cqi[3], C1_cqi[4], C1_cqi[5], C1_cqi[6], C1_cqi[7], C1_cqi[8]);
G1_q_a[2]_PORT_B_address_reg = DFFE(G1_q_a[2]_PORT_B_address, G1_q_a[2]_clock_0, , , );
G1_q_a[2]_PORT_A_write_enable = wren;
G1_q_a[2]_PORT_A_write_enable_reg = DFFE(G1_q_a[2]_PORT_A_write_enable, G1_q_a[2]_clock_0, , , );
G1_q_a[2]_clock_0 = C1L1;
G1_q_a[2]_PORT_A_data_out = MEMORY(G1_q_a[2]_PORT_A_data_in_reg, , G1_q_a[2]_PORT_A_address_reg, G1_q_a[2]_PORT_B_address_reg, G1_q_a[2]_PORT_A_write_enable_reg, , , , G1_q_a[2]_clock_0, , , , , );
G1_q_a[2] = G1_q_a[2]_PORT_A_data_out[0];


--G1_q_a[1] is ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[1]