shujucaiji.hier_info

通过ADC0809对模拟信号进行采样

|shujucaiji
ale <= adcint:inst.ale
clk => adcint:inst.clk
clk => cnt10b:inst1.clk
clk => lpm_conter8:inst3.clock
eoc => adcint:inst.eoc
d[0] => adcint:inst.d[0]
d[1] => adcint:inst.d[1]
d[2] => adcint:inst.d[2]
d[3] => adcint:inst.d[3]
d[4] => adcint:inst.d[4]
d[5] => adcint:inst.d[5]
d[6] => adcint:inst.d[6]
d[7] => adcint:inst.d[7]
start <= adcint:inst.start
oe <= adcint:inst.oe
adda <= adcint:inst.adda
lock0 <= adcint:inst.lock0
inclock <= cnt10b:inst1.clkout
clr => cnt10b:inst1.clr
wren => cnt10b:inst1.we
wren => inst4.IN0
wren => ram8b:inst2.wren
address[0] <= cnt10b:inst1.dout[0]
address[1] <= cnt10b:inst1.dout[1]
address[2] <= cnt10b:inst1.dout[2]
address[3] <= cnt10b:inst1.dout[3]
address[4] <= cnt10b:inst1.dout[4]
address[5] <= cnt10b:inst1.dout[5]
address[6] <= cnt10b:inst1.dout[6]
address[7] <= cnt10b:inst1.dout[7]
address[8] <= cnt10b:inst1.dout[8]
joc[0] <= lpm_conter8:inst3.q[0]
joc[1] <= lpm_conter8:inst3.q[1]
joc[2] <= lpm_conter8:inst3.q[2]
joc[3] <= lpm_conter8:inst3.q[3]
joc[4] <= lpm_conter8:inst3.q[4]
joc[5] <= lpm_conter8:inst3.q[5]
joc[6] <= lpm_conter8:inst3.q[6]
joc[7] <= lpm_conter8:inst3.q[7]
q[0] <= ram8b:inst2.q[0]
q[1] <= ram8b:inst2.q[1]
q[2] <= ram8b:inst2.q[2]
q[3] <= ram8b:inst2.q[3]
q[4] <= ram8b:inst2.q[4]
q[5] <= ram8b:inst2.q[5]
q[6] <= ram8b:inst2.q[6]
q[7] <= ram8b:inst2.q[7]


|shujucaiji|adcint:inst
d[0] => regl[0].DATAIN
d[1] => regl[1].DATAIN
d[2] => regl[2].DATAIN
d[3] => regl[3].DATAIN
d[4] => regl[4].DATAIN
d[5] => regl[5].DATAIN
d[6] => regl[6].DATAIN
d[7] => regl[7].DATAIN
clk => current_state~0.IN1
eoc => next_state.st3.DATAB
eoc => next_state.st2.IN2
ale <= current_state.st1.DB_MAX_OUTPUT_PORT_TYPE
start <= current_state.st1.DB_MAX_OUTPUT_PORT_TYPE
oe <= oe~0.DB_MAX_OUTPUT_PORT_TYPE
adda <= <VCC>
lock0 <= current_state.st4.DB_MAX_OUTPUT_PORT_TYPE
q[0] <= regl[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= regl[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= regl[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= regl[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= regl[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= regl[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= regl[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= regl[7].DB_MAX_OUTPUT_PORT_TYPE


|shujucaiji|cnt10b:inst1
lock0 => clk0~0.DATAB
clr => cqi[7].ACLR
clr => cqi[6].ACLR
clr => cqi[5].ACLR
clr => cqi[4].ACLR
clr => cqi[3].ACLR
clr => cqi[2].ACLR
clr => cqi[1].ACLR
clr => cqi[0].ACLR
clr => cqi[8].ACLR
clk => clk0~0.DATAA
we => clk0~0.OUTPUTSELECT
dout[0] <= cqi[0].DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= cqi[1].DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= cqi[2].DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= cqi[3].DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= cqi[4].DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= cqi[5].DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= cqi[6].DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= cqi[7].DB_MAX_OUTPUT_PORT_TYPE
dout[8] <= cqi[8].DB_MAX_OUTPUT_PORT_TYPE
clkout <= clk0~0.DB_MAX_OUTPUT_PORT_TYPE


|shujucaiji|lpm_conter8:inst3
clk_en => lpm_counter:lpm_counter_component.clk_en
clock => lpm_counter:lpm_counter_component.clock
q[0] <= lpm_counter:lpm_counter_component.q[0]
q[1] <= lpm_counter:lpm_counter_component.q[1]
q[2] <= lpm_counter:lpm_counter_component.q[2]
q[3] <= lpm_counter:lpm_counter_component.q[3]
q[4] <= lpm_counter:lpm_counter_component.q[4]
q[5] <= lpm_counter:lpm_counter_component.q[5]
q[6] <= lpm_counter:lpm_counter_component.q[6]
q[7] <= lpm_counter:lpm_counter_component.q[7]


|shujucaiji|lpm_conter8:inst3|lpm_counter:lpm_counter_component
clock => cntr_73e:auto_generated.clock
clk_en => cntr_73e:auto_generated.clk_en
cnt_en => ~NO_FANOUT~
updown => ~NO_FANOUT~
aclr => ~NO_FANOUT~
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
sconst => ~NO_FANOUT~
sload => ~NO_FANOUT~
data[0] => ~NO_FANOUT~
data[1] => ~NO_FANOUT~
data[2] => ~NO_FANOUT~
data[3] => ~NO_FANOUT~
data[4] => ~NO_FANOUT~
data[5] => ~NO_FANOUT~
data[6] => ~NO_FANOUT~
data[7] => ~NO_FANOUT~
cin => ~NO_FANOUT~
q[0] <= cntr_73e:auto_generated.q[0]
q[1] <= cntr_73e:auto_generated.q[1]
q[2] <= cntr_73e:auto_generated.q[2]
q[3] <= cntr_73e:auto_generated.q[3]
q[4] <= cntr_73e:auto_generated.q[4]
q[5] <= cntr_73e:auto_generated.q[5]
q[6] <= cntr_73e:auto_generated.q[6]
q[7] <= cntr_73e:auto_generated.q[7]
cout <= <GND>
eq[0] <= <GND>
eq[1] <= <GND>
eq[2] <= <GND>
eq[3] <= <GND>
eq[4] <= <GND>
eq[5] <= <GND>
eq[6] <= <GND>
eq[7] <= <GND>
eq[8] <= <GND>
eq[9] <= <GND>
eq[10] <= <GND>
eq[11] <= <GND>
eq[12] <= <GND>
eq[13] <= <GND>
eq[14] <= <GND>
eq[15] <= <GND>


|shujucaiji|lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated
clk_en => counter_cella0.ENA
clk_en => counter_cella1.ENA
clk_en => counter_cella2.ENA
clk_en => counter_cella3.ENA
clk_en => counter_cella4.ENA
clk_en => counter_cella5.ENA
clk_en => counter_cella6.ENA
clk_en => counter_cella7.ENA
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
clock => counter_cella4.CLK
clock => counter_cella5.CLK
clock => counter_cella6.CLK
clock => counter_cella7.CLK
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
q[4] <= counter_cella4.REGOUT
q[5] <= counter_cella5.REGOUT
q[6] <= counter_cella6.REGOUT
q[7] <= counter_cella7.REGOUT


|shujucaiji|ram8b:inst2
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
address[8] => altsyncram:altsyncram_component.address_a[8]
data[0] => altsyncram:altsyncram_component.data_a[0]
data[1] => altsyncram:altsyncram_component.data_a[1]
data[2] => altsyncram:altsyncram_component.data_a[2]
data[3] => altsyncram:altsyncram_component.data_a[3]
data[4] => altsyncram:altsyncram_component.data_a[4]
data[5] => altsyncram:altsyncram_component.data_a[5]
data[6] => altsyncram:altsyncram_component.data_a[6]
data[7] => altsyncram:altsyncram_component.data_a[7]
inclock => altsyncram:altsyncram_component.clock0
wren => altsyncram:altsyncram_component.wren_a
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]


|shujucaiji|ram8b:inst2|altsyncram:altsyncram_component
wren_a => altsyncram_gn51:auto_generated.wren_a
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_gn51:auto_generated.data_a[0]
data_a[1] => altsyncram_gn51:auto_generated.data_a[1]
data_a[2] => altsyncram_gn51:auto_generated.data_a[2]
data_a[3] => altsyncram_gn51:auto_generated.data_a[3]
data_a[4] => altsyncram_gn51:auto_generated.data_a[4]
data_a[5] => altsyncram_gn51:auto_generated.data_a[5]
data_a[6] => altsyncram_gn51:auto_generated.data_a[6]
data_a[7] => altsyncram_gn51:auto_generated.data_a[7]
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_gn51:auto_generated.address_a[0]
address_a[1] => altsyncram_gn51:auto_generated.address_a[1]
address_a[2] => altsyncram_gn51:auto_generated.address_a[2]
address_a[3] => altsyncram_gn51:auto_generated.address_a[3]
address_a[4] => altsyncram_gn51:auto_generated.address_a[4]
address_a[5] => altsyncram_gn51:auto_generated.address_a[5]
address_a[6] => altsyncram_gn51:auto_generated.address_a[6]
address_a[7] => altsyncram_gn51:auto_generated.address_a[7]
address_a[8] => altsyncram_gn51:auto_generated.address_a[8]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_gn51:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_gn51:auto_generated.q_a[0]
q_a[1] <= altsyncram_gn51:auto_generated.q_a[1]
q_a[2] <= altsyncram_gn51:auto_generated.q_a[2]
q_a[3] <= altsyncram_gn51:auto_generated.q_a[3]
q_a[4] <= altsyncram_gn51:auto_generated.q_a[4]
q_a[5] <= altsyncram_gn51:auto_generated.q_a[5]
q_a[6] <= altsyncram_gn51:auto_generated.q_a[6]
q_a[7] <= altsyncram_gn51:auto_generated.q_a[7]
q_b[0] <= <GND>


|shujucaiji|ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
wren_a => ram_block1a0.PORTAWE
wren_a => ram_block1a1.PORTAWE
wren_a => ram_block1a2.PORTAWE
wren_a => ram_block1a3.PORTAWE
wren_a => ram_block1a4.PORTAWE
wren_a => ram_block1a5.PORTAWE
wren_a => ram_block1a6.PORTAWE
wren_a => ram_block1a7.PORTAWE