shujucaiji.tan.qmsg

通过ADC0809对模拟信号进行采样

{ "Info" "ITDB_TSU_RESULT" "lpm_conter8:inst3\|lpm_counter:lpm_counter_component\|cntr_73e:auto_generated\|safe_q\[7\] wren clk 4.724 ns register " "Info: tsu for register \"lpm_conter8:inst3\|lpm_counter:lpm_counter_component\|cntr_73e:auto_generated\|safe_q\[7\]\" (data pin = \"wren\", clock pin = \"clk\") is 4.724 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.454 ns + Longest pin register " "Info: + Longest pin to register delay is 7.454 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns wren 1 CLK PIN_132 10 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_132; Fanout = 10; CLK Node = 'wren'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shujucaiji" "UNKNOWN" "V1" "D:/shujucaiji/db/shujucaiji.quartus_db" { Floorplan "D:/shujucaiji/" "" "" { wren } "NODE_NAME" } "" } } { "shujucaiji.bdf" "" { Schematic "D:/shujucaiji/shujucaiji.bdf" { { 264 48 216 280 "wren" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.112 ns) + CELL(0.867 ns) 7.454 ns lpm_conter8:inst3\|lpm_counter:lpm_counter_component\|cntr_73e:auto_generated\|safe_q\[7\] 2 REG LC_X7_Y12_N7 2 " "Info: 2: + IC(5.112 ns) + CELL(0.867 ns) = 7.454 ns; Loc. = LC_X7_Y12_N7; Fanout = 2; REG Node = 'lpm_conter8:inst3\|lpm_counter:lpm_counter_component\|cntr_73e:auto_generated\|safe_q\[7\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shujucaiji" "UNKNOWN" "V1" "D:/shujucaiji/db/shujucaiji.quartus_db" { Floorplan "D:/shujucaiji/" "" "5.979 ns" { wren lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated|safe_q[7] } "NODE_NAME" } "" } } { "db/cntr_73e.tdf" "" { Text "D:/shujucaiji/db/cntr_73e.tdf" 98 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.342 ns ( 31.42 % ) " "Info: Total cell delay = 2.342 ns ( 31.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.112 ns ( 68.58 % ) " "Info: Total interconnect delay = 5.112 ns ( 68.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shujucaiji" "UNKNOWN" "V1" "D:/shujucaiji/db/shujucaiji.quartus_db" { Floorplan "D:/shujucaiji/" "" "7.454 ns" { wren lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated|safe_q[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.454 ns" { wren wren~out0 lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated|safe_q[7] } { 0.000ns 0.000ns 5.112ns } { 0.000ns 1.475ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "db/cntr_73e.tdf" "" { Text "D:/shujucaiji/db/cntr_73e.tdf" 98 8 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.767 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.767 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 14 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 14; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shujucaiji" "UNKNOWN" "V1" "D:/shujucaiji/db/shujucaiji.quartus_db" { Floorplan "D:/shujucaiji/" "" "" { clk } "NODE_NAME" } "" } } { "shujucaiji.bdf" "" { Schematic "D:/shujucaiji/shujucaiji.bdf" { { 144 48 216 160 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.587 ns) + CELL(0.711 ns) 2.767 ns lpm_conter8:inst3\|lpm_counter:lpm_counter_component\|cntr_73e:auto_generated\|safe_q\[7\] 2 REG LC_X7_Y12_N7 2 " "Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X7_Y12_N7; Fanout = 2; REG Node = 'lpm_conter8:inst3\|lpm_counter:lpm_counter_component\|cntr_73e:auto_generated\|safe_q\[7\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shujucaiji" "UNKNOWN" "V1" "D:/shujucaiji/db/shujucaiji.quartus_db" { Floorplan "D:/shujucaiji/" "" "1.298 ns" { clk lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated|safe_q[7] } "NODE_NAME" } "" } } { "db/cntr_73e.tdf" "" { Text "D:/shujucaiji/db/cntr_73e.tdf" 98 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.79 % ) " "Info: Total cell delay = 2.180 ns ( 78.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.587 ns ( 21.21 % ) " "Info: Total interconnect delay = 0.587 ns ( 21.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shujucaiji" "UNKNOWN" "V1" "D:/shujucaiji/db/shujucaiji.quartus_db" { Floorplan "D:/shujucaiji/" "" "2.767 ns" { clk lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated|safe_q[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.767 ns" { clk clk~out0 lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated|safe_q[7] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shujucaiji" "UNKNOWN" "V1" "D:/shujucaiji/db/shujucaiji.quartus_db" { Floorplan "D:/shujucaiji/" "" "7.454 ns" { wren lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated|safe_q[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.454 ns" { wren wren~out0 lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated|safe_q[7] } { 0.000ns 0.000ns 5.112ns } { 0.000ns 1.475ns 0.867ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shujucaiji" "UNKNOWN" "V1" "D:/shujucaiji/db/shujucaiji.quartus_db" { Floorplan "D:/shujucaiji/" "" "2.767 ns" { clk lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated|safe_q[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.767 ns" { clk clk~out0 lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated|safe_q[7] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk q\[2\] ram8b:inst2\|altsyncram:altsyncram_component\|altsyncram_gn51:auto_generated\|ram_block1a7~porta_address_reg0 20.195 ns memory " "Info: tco from clock \"clk\" to destination pin \"q\[2\]\" through memory \"ram8b:inst2\|altsyncram:altsyncram_component\|altsyncram_gn51:auto_generated\|ram_block1a7~porta_address_reg0\" is 20.195 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 10.381 ns + Longest memory " "Info: + Longest clock path from clock \"clk\" to source memory is 10.381 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 14 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 14; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shujucaiji" "UNKNOWN" "V1" "D:/shujucaiji/db/shujucaiji.quartus_db" { Floorplan "D:/shujucaiji/" "" "" { clk } "NODE_NAME" } "" } } { "shujucaiji.bdf" "" { Schematic "D:/shujucaiji/shujucaiji.bdf" { { 144 48 216 160 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.558 ns) + CELL(0.935 ns) 2.962 ns adcint:inst\|current_state.st4 2 REG LC_X9_Y6_N4 12 " "Info: 2: + IC(0.558 ns) + CELL(0.935 ns) = 2.962 ns; Loc. = LC_X9_Y6_N4; Fanout = 12; REG Node = 'adcint:inst\|current_state.st4'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shujucaiji" "UNKNOWN" "V1" "D:/shujucaiji/db/shujucaiji.quartus_db" { Floorplan "D:/shujucaiji/" "" "1.493 ns" { clk adcint:inst|current_state.st4 } "NODE_NAME" } "" } } { "adcint.vhd" "" { Text "D:/shujucaiji/adcint.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.993 ns) + CELL(0.292 ns) 5.247 ns cnt10b:inst1\|clkout~7 3 COMB LC_X7_Y12_N8 36 " "Info: 3: + IC(1.993 ns) + CELL(0.292 ns) = 5.247 ns; Loc. = LC_X7_Y12_N8; Fanout = 36; COMB Node = 'cnt10b:inst1\|clkout~7'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shujucaiji" "UNKNOWN" "V1" "D:/shujucaiji/db/shujucaiji.quartus_db" { Floorplan "D:/shujucaiji/" "" "2.285 ns" { adcint:inst|current_state.st4 cnt10b:inst1|clkout~7 } "NODE_NAME" } "" } } { "cnt10b.vhd" "" { Text "D:/shujucaiji/cnt10b.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.412 ns) + CELL(0.722 ns) 10.381 ns ram8b:inst2\|altsyncram:altsyncram_component\|altsyncram_gn51:auto_generated\|ram_block1a7~porta_address_reg0 4 MEM M4K_X13_Y12 8 " "Info: 4: + IC(4.412 ns) + CELL(0.722 ns) = 10.381 ns; Loc. = M4K_X13_Y12; Fanout = 8; MEM Node = 'ram8b:inst2\|altsyncram:altsyncram_component\|altsyncram_gn51:auto_generated\|ram_block1a7~porta_address_reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shujucaiji" "UNKNOWN" "V1" "D:/shujucaiji/db/shujucaiji.quartus_db" { Floorplan "D:/shujucaiji/" "" "5.134 ns" { cnt10b:inst1|clkout~7 ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_gn51.tdf" "" { Text "D:/shujucaiji/db/altsyncram_gn51.tdf" 185 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.418 ns ( 32.93 % ) " "Info: Total cell delay = 3.418 ns ( 32.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.963 ns ( 67.07 % ) " "Info: Total interconnect delay = 6.963 ns ( 67.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shujucaiji" "UNKNOWN" "V1" "D:/shujucaiji/db/shujucaiji.quartus_db" { Floorplan "D:/shujucaiji/" "" "10.381 ns" { clk adcint:inst|current_state.st4 cnt10b:inst1|clkout~7 ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "10.381 ns" { clk clk~out0 adcint:inst|current_state.st4 cnt10b:inst1|clkout~7 ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_address_reg0 } { 0.000ns 0.000ns 0.558ns 1.993ns 4.412ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.722ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_gn51.tdf" "" { Text "D:/shujucaiji/db/altsyncram_gn51.tdf" 185 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.164 ns + Longest memory pin " "Info: + Longest memory to pin delay is 9.164 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ram8b:inst2\|altsyncram:altsyncram_component\|altsyncram_gn51:auto_generated\|ram_block1a7~porta_address_reg0 1 MEM M4K_X13_Y12 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y12; Fanout = 8; MEM Node = 'ram8b:inst2\|altsyncram:altsyncram_component\|altsyncram_gn51:auto_generated\|ram_block1a7~porta_address_reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shujucaiji" "UNKNOWN" "V1" "D:/shujucaiji/db/shujucaiji.quartus_db" { Floorplan "D:/shujucaiji/" "" "" { ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_gn51.tdf" "" { Text "D:/shujucaiji/db/altsyncram_gn51.tdf" 185 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.308 ns) 4.308 ns ram8b:inst2\|altsyncram:altsyncram_component\|altsyncram_gn51:auto_generated\|q_a\[2\] 2 MEM M4K_X13_Y12 1 " "Info: 2: + IC(0.000 ns) + CELL(4.308 ns) = 4.308 ns; Loc. = M4K_X13_Y12; Fanout =