shujucaiji.tan.qmsg

通过ADC0809对模拟信号进行采样

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "shujucaiji.bdf" "" { Schematic "D:/shujucaiji/shujucaiji.bdf" { { 144 48 216 160 "clk" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "wren " "Info: Assuming node \"wren\" is an undefined clock" {  } { { "shujucaiji.bdf" "" { Schematic "D:/shujucaiji/shujucaiji.bdf" { { 264 48 216 280 "wren" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "wren" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "cnt10b:inst1\|clkout~7 " "Info: Detected gated clock \"cnt10b:inst1\|clkout~7\" as buffer" {  } { { "cnt10b.vhd" "" { Text "D:/shujucaiji/cnt10b.vhd" 7 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "cnt10b:inst1\|clkout~7" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "adcint:inst\|current_state.st4 " "Info: Detected ripple clock \"adcint:inst\|current_state.st4\" as buffer" {  } { { "adcint.vhd" "" { Text "D:/shujucaiji/adcint.vhd" 39 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "adcint:inst\|current_state.st4" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk memory ram8b:inst2\|altsyncram:altsyncram_component\|altsyncram_gn51:auto_generated\|ram_block1a7~porta_datain_reg7 memory ram8b:inst2\|altsyncram:altsyncram_component\|altsyncram_gn51:auto_generated\|ram_block1a7~porta_memory_reg7 136.82 MHz 7.309 ns Internal " "Info: Clock \"clk\" has Internal fmax of 136.82 MHz between source memory \"ram8b:inst2\|altsyncram:altsyncram_component\|altsyncram_gn51:auto_generated\|ram_block1a7~porta_datain_reg7\" and destination memory \"ram8b:inst2\|altsyncram:altsyncram_component\|altsyncram_gn51:auto_generated\|ram_block1a7~porta_memory_reg7\" (period= 7.309 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.319 ns + Longest memory memory " "Info: + Longest memory to memory delay is 4.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ram8b:inst2\|altsyncram:altsyncram_component\|altsyncram_gn51:auto_generated\|ram_block1a7~porta_datain_reg7 1 MEM M4K_X13_Y12 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y12; Fanout = 1; MEM Node = 'ram8b:inst2\|altsyncram:altsyncram_component\|altsyncram_gn51:auto_generated\|ram_block1a7~porta_datain_reg7'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shujucaiji" "UNKNOWN" "V1" "D:/shujucaiji/db/shujucaiji.quartus_db" { Floorplan "D:/shujucaiji/" "" "" { ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_datain_reg7 } "NODE_NAME" } "" } } { "db/altsyncram_gn51.tdf" "" { Text "D:/shujucaiji/db/altsyncram_gn51.tdf" 185 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.319 ns) 4.319 ns ram8b:inst2\|altsyncram:altsyncram_component\|altsyncram_gn51:auto_generated\|ram_block1a7~porta_memory_reg7 2 MEM M4K_X13_Y12 0 " "Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X13_Y12; Fanout = 0; MEM Node = 'ram8b:inst2\|altsyncram:altsyncram_component\|altsyncram_gn51:auto_generated\|ram_block1a7~porta_memory_reg7'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shujucaiji" "UNKNOWN" "V1" "D:/shujucaiji/db/shujucaiji.quartus_db" { Floorplan "D:/shujucaiji/" "" "4.319 ns" { ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_datain_reg7 ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_memory_reg7 } "NODE_NAME" } "" } } { "db/altsyncram_gn51.tdf" "" { Text "D:/shujucaiji/db/altsyncram_gn51.tdf" 185 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.319 ns ( 100.00 % ) " "Info: Total cell delay = 4.319 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shujucaiji" "UNKNOWN" "V1" "D:/shujucaiji/db/shujucaiji.quartus_db" { Floorplan "D:/shujucaiji/" "" "4.319 ns" { ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_datain_reg7 ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_memory_reg7 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.319 ns" { ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_datain_reg7 ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_memory_reg7 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-2.247 ns - Smallest " "Info: - Smallest clock skew is -2.247 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.134 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk\" to destination memory is 8.134 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 14 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 14; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shujucaiji" "UNKNOWN" "V1" "D:/shujucaiji/db/shujucaiji.quartus_db" { Floorplan "D:/shujucaiji/" "" "" { clk } "NODE_NAME" } "" } } { "shujucaiji.bdf" "" { Schematic "D:/shujucaiji/shujucaiji.bdf" { { 144 48 216 160 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.103 ns) + CELL(0.442 ns) 3.014 ns cnt10b:inst1\|clkout~7 2 COMB LC_X7_Y12_N8 36 " "Info: 2: + IC(1.103 ns) + CELL(0.442 ns) = 3.014 ns; Loc. = LC_X7_Y12_N8; Fanout = 36; COMB Node = 'cnt10b:inst1\|clkout~7'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shujucaiji" "UNKNOWN" "V1" "D:/shujucaiji/db/shujucaiji.quartus_db" { Floorplan "D:/shujucaiji/" "" "1.545 ns" { clk cnt10b:inst1|clkout~7 } "NODE_NAME" } "" } } { "cnt10b.vhd" "" { Text "D:/shujucaiji/cnt10b.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.412 ns) + CELL(0.708 ns) 8.134 ns ram8b:inst2\|altsyncram:altsyncram_component\|altsyncram_gn51:auto_generated\|ram_block1a7~porta_memory_reg7 3 MEM M4K_X13_Y12 0 " "Info: 3: + IC(4.412 ns) + CELL(0.708 ns) = 8.134 ns; Loc. = M4K_X13_Y12; Fanout = 0; MEM Node = 'ram8b:inst2\|altsyncram:altsyncram_component\|altsyncram_gn51:auto_generated\|ram_block1a7~porta_memory_reg7'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shujucaiji" "UNKNOWN" "V1" "D:/shujucaiji/db/shujucaiji.quartus_db" { Floorplan "D:/shujucaiji/" "" "5.120 ns" { cnt10b:inst1|clkout~7 ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_memory_reg7 } "NODE_NAME" } "" } } { "db/altsyncram_gn51.tdf" "" { Text "D:/shujucaiji/db/altsyncram_gn51.tdf" 185 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.619 ns ( 32.20 % ) " "Info: Total cell delay = 2.619 ns ( 32.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.515 ns ( 67.80 % ) " "Info: Total interconnect delay = 5.515 ns ( 67.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shujucaiji" "UNKNOWN" "V1" "D:/shujucaiji/db/shujucaiji.quartus_db" { Floorplan "D:/shujucaiji/" "" "8.134 ns" { clk cnt10b:inst1|clkout~7 ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_memory_reg7 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.134 ns" { clk clk~out0 cnt10b:inst1|clkout~7 ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_memory_reg7 } { 0.000ns 0.000ns 1.103ns 4.412ns } { 0.000ns 1.469ns 0.442ns 0.708ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 10.381 ns - Longest memory " "Info: - Longest clock path from clock \"clk\" to source memory is 10.381 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 14 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 14; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shujucaiji" "UNKNOWN" "V1" "D:/shujucaiji/db/shujucaiji.quartus_db" { Floorplan "D:/shujucaiji/" "" "" { clk } "NODE_NAME" } "" } } { "shujucaiji.bdf" "" { Schematic "D:/shujucaiji/shujucaiji.bdf" { { 144 48 216 160 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.558 ns) + CELL(0.935 ns) 2.962 ns adcint:inst\|current_state.st4 2 REG LC_X9_Y6_N4 12 " "Info: 2: + IC(0.558 ns) + CELL(0.935 ns) = 2.962 ns; Loc. = LC_X9_Y6_N4; Fanout = 12; REG Node = 'adcint:inst\|current_state.st4'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shujucaiji" "UNKNOWN" "V1" "D:/shujucaiji/db/shujucaiji.quartus_db" { Floorplan "D:/shujucaiji/" "" "1.493 ns" { clk adcint:inst|current_state.st4 } "NODE_NAME" } "" } } { "adcint.vhd" "" { Text "D:/shujucaiji/adcint.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.993 ns) + CELL(0.292 ns) 5.247 ns cnt10b:inst1\|clkout~7 3 COMB LC_X7_Y12_N8 36 " "Info: 3: + IC(1.993 ns) + CELL(0.292 ns) = 5.247 ns; Loc. = LC_X7_Y12_N8; Fanout = 36; COMB Node = 'cnt10b:inst1\|clkout~7'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shujucaiji" "UNKNOWN" "V1" "D:/shujucaiji/db/shujucaiji.quartus_db" { Floorplan "D:/shujucaiji/" "" "2.285 ns" { adcint:inst|current_state.st4 cnt10b:inst1|clkout~7 } "NODE_NAME" } "" } } { "cnt10b.vhd" "" { Text "D:/shujucaiji/cnt10b.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.412 ns) + CELL(0.722 ns) 10.381 ns ram8b:inst2\|altsyncram:altsyncram_component\|altsyncram_gn51:auto_generated\|ram_block1a7~porta_datain_reg7 4 MEM M4K_X13_Y12 1 " "Info: 4: + IC(4.412 ns) + CELL(0.722 ns) = 10.381 ns; Loc. = M4K_X13_Y12; Fanout = 1; MEM Node = 'ram8b:inst2\|altsyncram:altsyncram_component\|altsyncram_gn51:auto_generated\|ram_block1a7~porta_datain_reg7'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shujucaiji" "UNKNOWN" "V1" "D:/shujucaiji/db/shujucaiji.quartus_db" { Floorplan "D:/shujucaiji/" "" "5.134 ns" { cnt10b:inst1|clkout~7 ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_datain_reg7 } "NODE_NAME" } "" } } { "db/altsyncram_gn51.tdf" "" { Text "D:/shujucaiji/db/altsyncram_gn51.tdf" 185 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.418 ns ( 32.93 % ) " "Info: Total cell delay = 3.418 ns ( 32.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.963 ns ( 67.07 % ) " "Info: Total interconnect delay = 6.963 ns ( 67.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shujucaiji" "UNKNOWN" "V1" "D:/shujucaiji/db/shujucaiji.quartus_db" { Floorplan "D:/shujucaiji/" "" "10.381 ns" { clk adcint:inst|current_state.st4 cnt10b:inst1|clkout~7 ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_datain_reg7 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "10.381 ns" { clk clk~out0 adcint:inst|current_state.st4 cnt10b:inst1|clkout~7 ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_datain_reg7 } { 0.000ns 0.000ns 0.558ns 1.993ns 4.412ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.722ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shujucaiji" "UNKNOWN" "V1" "D:/shujucaiji/db/shujucaiji.quartus_db" { Floorplan "D:/shujucaiji/" "" "8.134 ns" { clk cnt10b:inst1|clkout~7 ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_memory_reg7 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.134 ns" { clk clk~out0 cnt10b:inst1|clkout~7 ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_memory_reg7 } { 0.000ns 0.000ns 1.103ns 4.412ns } { 0.000ns 1.469ns 0.442ns 0.708ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shujucaiji" "UNKNOWN" "V1" "D:/shujucaiji/db/shujucaiji.quartus_db" { Floorplan "D:/shujucaiji/" "" "10.381 ns" { clk adcint:inst|current_state.st4 cnt10b:inst1|clkout~7 ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_datain_reg7 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "10.381 ns" { clk clk~out0 adcint:inst|current_state.st4 cnt10b:inst1|clkout~7 ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_datain_reg7 } { 0.000ns 0.000ns 0.558ns 1.993ns 4.412ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.722ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_gn51.tdf" "" { Text "D:/shujucaiji/db/altsyncram_gn51.tdf" 185 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_gn51.tdf" "" { Text "D:/shujucaiji/db/altsyncram_gn51.tdf" 185 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shujucaiji" "UNKNOWN" "V1" "D:/shujucaiji/db/shujucaiji.quartus_db" { Floorplan "D:/shujucaiji/" "" "4.319 ns" { ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_datain_reg7 ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_memory_reg7 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.319 ns" { ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_datain_reg7 ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_memory_reg7 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shujucaiji" "UNKNOWN" "V1" "D:/shujucaiji/db/shujucaiji.quartus_db" { Floorplan "D:/shujucaiji/" "" "8.134 ns" { clk cnt10b:inst1|clkout~7 ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_memory_reg7 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.134 ns" { clk clk~out0 cnt10b:inst1|clkout~7 ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_memory_reg7 } { 0.000ns 0.000ns 1.103ns 4.412ns } { 0.000ns 1.469ns 0.442ns 0.708ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shujucaiji" "UNKNOWN" "V1" "D:/shujucaiji/db/shujucaiji.quartus_db" { Floorplan "D:/shujucaiji/" "" "10.381 ns" { clk adcint:inst|current_state.st4 cnt10b:inst1|clkout~7 ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_datain_reg7 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "10.381 ns" { clk clk~out0 adcint:inst|current_state.st4 cnt10b:inst1|clkout~7 ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_datain_reg7 } { 0.000ns 0.000ns 0.558ns 1.993ns 4.412ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.722ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}