shujucaiji.tan.summary

通过ADC0809对模拟信号进行采样

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.724 ns
From           : wren
To             : lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated|safe_q[0]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 20.195 ns
From           : ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_address_reg8
To             : q[2]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 7.291 ns
From           : clk
To             : inclock
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 2.555 ns
From           : wren
To             : ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_we_reg
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 136.82 MHz ( period = 7.309 ns )
From           : ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_datain_reg0
To             : ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_memory_reg0
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'wren'
Slack          : N/A
Required Time  : None
Actual Time    : 197.01 MHz ( period = 5.076 ns )
From           : ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_datain_reg0
To             : ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_memory_reg0
From Clock     : wren
To Clock       : wren
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : adcint:inst|regl[7]
To             : ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_datain_reg0
From Clock     : clk
To Clock       : clk
Failed Paths   : 49

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 49

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