shujucaiji.tan.rpt

通过ADC0809对模拟信号进行采样

; Worst-case tco               ; N/A                                      ; None          ; 20.195 ns                        ; ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_address_reg8 ; q[2]                                                                                                      ; clk        ; --       ; 0            ;
; Worst-case tpd               ; N/A                                      ; None          ; 7.291 ns                         ; clk                                                                                                        ; inclock                                                                                                   ; --         ; --       ; 0            ;
; Worst-case th                ; N/A                                      ; None          ; 2.555 ns                         ; wren                                                                                                       ; ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_we_reg      ; --         ; clk      ; 0            ;
; Clock Setup: 'clk'           ; N/A                                      ; None          ; 136.82 MHz ( period = 7.309 ns ) ; ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_datain_reg0  ; ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_memory_reg0 ; clk        ; clk      ; 0            ;
; Clock Setup: 'wren'          ; N/A                                      ; None          ; 197.01 MHz ( period = 5.076 ns ) ; ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_datain_reg0  ; ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_memory_reg0 ; wren       ; wren     ; 0            ;
; Clock Hold: 'clk'            ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; adcint:inst|regl[7]                                                                                        ; ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_datain_reg0 ; clk        ; clk      ; 49           ;
; Total number of failed paths ;                                          ;               ;                                  ;                                                                                                            ;                                                                                                           ;            ;          ; 49           ;
+------------------------------+------------------------------------------+---------------+----------------------------------+------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C3T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; wren            ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                                                                                                          ;
+-------+------------------------------------------------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+