shujucaiji.fit.eqn

通过ADC0809对模拟信号进行采样

G1_q_a[2] = G1_q_a[7]_PORT_A_data_out[5];

--G1_q_a[3] is ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[3] at M4K_X13_Y12
G1_q_a[7]_PORT_A_data_in = BUS(B1_regl[7], B1_regl[6], B1_regl[5], B1_regl[4], B1_regl[3], B1_regl[2], B1_regl[1], B1_regl[0]);
G1_q_a[7]_PORT_A_data_in_reg = DFFE(G1_q_a[7]_PORT_A_data_in, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_PORT_A_address = BUS(C1_cqi[0], C1_cqi[1], C1_cqi[2], C1_cqi[3], C1_cqi[4], C1_cqi[5], C1_cqi[6], C1_cqi[7], C1_cqi[8]);
G1_q_a[7]_PORT_A_address_reg = DFFE(G1_q_a[7]_PORT_A_address, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_PORT_A_write_enable = wren;
G1_q_a[7]_PORT_A_write_enable_reg = DFFE(G1_q_a[7]_PORT_A_write_enable, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_clock_0 = GLOBAL(C1L1);
G1_q_a[7]_PORT_A_data_out = MEMORY(G1_q_a[7]_PORT_A_data_in_reg, , G1_q_a[7]_PORT_A_address_reg, , G1_q_a[7]_PORT_A_write_enable_reg, , , , G1_q_a[7]_clock_0, , , , , );
G1_q_a[3] = G1_q_a[7]_PORT_A_data_out[4];

--G1_q_a[4] is ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[4] at M4K_X13_Y12
G1_q_a[7]_PORT_A_data_in = BUS(B1_regl[7], B1_regl[6], B1_regl[5], B1_regl[4], B1_regl[3], B1_regl[2], B1_regl[1], B1_regl[0]);
G1_q_a[7]_PORT_A_data_in_reg = DFFE(G1_q_a[7]_PORT_A_data_in, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_PORT_A_address = BUS(C1_cqi[0], C1_cqi[1], C1_cqi[2], C1_cqi[3], C1_cqi[4], C1_cqi[5], C1_cqi[6], C1_cqi[7], C1_cqi[8]);
G1_q_a[7]_PORT_A_address_reg = DFFE(G1_q_a[7]_PORT_A_address, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_PORT_A_write_enable = wren;
G1_q_a[7]_PORT_A_write_enable_reg = DFFE(G1_q_a[7]_PORT_A_write_enable, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_clock_0 = GLOBAL(C1L1);
G1_q_a[7]_PORT_A_data_out = MEMORY(G1_q_a[7]_PORT_A_data_in_reg, , G1_q_a[7]_PORT_A_address_reg, , G1_q_a[7]_PORT_A_write_enable_reg, , , , G1_q_a[7]_clock_0, , , , , );
G1_q_a[4] = G1_q_a[7]_PORT_A_data_out[3];

--G1_q_a[5] is ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[5] at M4K_X13_Y12
G1_q_a[7]_PORT_A_data_in = BUS(B1_regl[7], B1_regl[6], B1_regl[5], B1_regl[4], B1_regl[3], B1_regl[2], B1_regl[1], B1_regl[0]);
G1_q_a[7]_PORT_A_data_in_reg = DFFE(G1_q_a[7]_PORT_A_data_in, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_PORT_A_address = BUS(C1_cqi[0], C1_cqi[1], C1_cqi[2], C1_cqi[3], C1_cqi[4], C1_cqi[5], C1_cqi[6], C1_cqi[7], C1_cqi[8]);
G1_q_a[7]_PORT_A_address_reg = DFFE(G1_q_a[7]_PORT_A_address, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_PORT_A_write_enable = wren;
G1_q_a[7]_PORT_A_write_enable_reg = DFFE(G1_q_a[7]_PORT_A_write_enable, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_clock_0 = GLOBAL(C1L1);
G1_q_a[7]_PORT_A_data_out = MEMORY(G1_q_a[7]_PORT_A_data_in_reg, , G1_q_a[7]_PORT_A_address_reg, , G1_q_a[7]_PORT_A_write_enable_reg, , , , G1_q_a[7]_clock_0, , , , , );
G1_q_a[5] = G1_q_a[7]_PORT_A_data_out[2];

--G1_q_a[6] is ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|q_a[6] at M4K_X13_Y12
G1_q_a[7]_PORT_A_data_in = BUS(B1_regl[7], B1_regl[6], B1_regl[5], B1_regl[4], B1_regl[3], B1_regl[2], B1_regl[1], B1_regl[0]);
G1_q_a[7]_PORT_A_data_in_reg = DFFE(G1_q_a[7]_PORT_A_data_in, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_PORT_A_address = BUS(C1_cqi[0], C1_cqi[1], C1_cqi[2], C1_cqi[3], C1_cqi[4], C1_cqi[5], C1_cqi[6], C1_cqi[7], C1_cqi[8]);
G1_q_a[7]_PORT_A_address_reg = DFFE(G1_q_a[7]_PORT_A_address, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_PORT_A_write_enable = wren;
G1_q_a[7]_PORT_A_write_enable_reg = DFFE(G1_q_a[7]_PORT_A_write_enable, G1_q_a[7]_clock_0, , , );
G1_q_a[7]_clock_0 = GLOBAL(C1L1);
G1_q_a[7]_PORT_A_data_out = MEMORY(G1_q_a[7]_PORT_A_data_in_reg, , G1_q_a[7]_PORT_A_address_reg, , G1_q_a[7]_PORT_A_write_enable_reg, , , , G1_q_a[7]_clock_0, , , , , );
G1_q_a[6] = G1_q_a[7]_PORT_A_data_out[1];


--B1_current_state.st0 is adcint:inst|current_state.st0 at LC_X9_Y6_N5
--operation mode is normal

B1_current_state.st0_lut_out = !B1_current_state.st4;
B1_current_state.st0 = DFFEAS(B1_current_state.st0_lut_out, GLOBAL(clk), VCC, , , , , , );


--B1_current_state.st2 is adcint:inst|current_state.st2 at LC_X9_Y6_N6
--operation mode is normal

B1_current_state.st2_lut_out = B1_current_state.st1 # B1_current_state.st2 & !eoc;
B1_current_state.st2 = DFFEAS(B1_current_state.st2_lut_out, GLOBAL(clk), VCC, , , , , , );


--B1_regl[7] is adcint:inst|regl[7] at LC_X17_Y12_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_regl[7]_lut_out = GND;
B1_regl[7] = DFFEAS(B1_regl[7]_lut_out, GLOBAL(B1_current_state.st4), VCC, , , d[7], , , VCC);


--B1_regl[6] is adcint:inst|regl[6] at LC_X16_Y11_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_regl[6]_lut_out = GND;
B1_regl[6] = DFFEAS(B1_regl[6]_lut_out, GLOBAL(B1_current_state.st4), VCC, , , d[6], , , VCC);


--B1_regl[5] is adcint:inst|regl[5] at LC_X12_Y11_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_regl[5]_lut_out = GND;
B1_regl[5] = DFFEAS(B1_regl[5]_lut_out, GLOBAL(B1_current_state.st4), VCC, , , d[5], , , VCC);


--B1_regl[4] is adcint:inst|regl[4] at LC_X11_Y12_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_regl[4]_lut_out = GND;
B1_regl[4] = DFFEAS(B1_regl[4]_lut_out, GLOBAL(B1_current_state.st4), VCC, , , d[4], , , VCC);


--B1_regl[3] is adcint:inst|regl[3] at LC_X10_Y12_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_regl[3]_lut_out = GND;
B1_regl[3] = DFFEAS(B1_regl[3]_lut_out, GLOBAL(B1_current_state.st4), VCC, , , d[3], , , VCC);


--B1_regl[2] is adcint:inst|regl[2] at LC_X8_Y9_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_regl[2]_lut_out = GND;
B1_regl[2] = DFFEAS(B1_regl[2]_lut_out, GLOBAL(B1_current_state.st4), VCC, , , d[2], , , VCC);


--B1_regl[1] is adcint:inst|regl[1] at LC_X15_Y12_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_regl[1]_lut_out = GND;
B1_regl[1] = DFFEAS(B1_regl[1]_lut_out, GLOBAL(B1_current_state.st4), VCC, , , d[1], , , VCC);


--B1_regl[0] is adcint:inst|regl[0] at LC_X16_Y12_N2
--operation mode is normal

B1_regl[0]_lut_out = d[0];
B1_regl[0] = DFFEAS(B1_regl[0]_lut_out, GLOBAL(B1_current_state.st4), VCC, , , , , , );


--clk is clk at PIN_17
--operation mode is input

clk = INPUT();


--wren is wren at PIN_132
--operation mode is input

wren = INPUT();


--eoc is eoc at PIN_47
--operation mode is input

eoc = INPUT();


--clr is clr at PIN_16
--operation mode is input

clr = INPUT();


--d[7] is d[7] at PIN_119
--operation mode is input

d[7] = INPUT();


--d[6] is d[6] at PIN_100
--operation mode is input

d[6] = INPUT();


--d[5] is d[5] at PIN_54
--operation mode is input

d[5] = INPUT();


--d[4] is d[4] at PIN_133
--operation mode is input

d[4] = INPUT();


--d[3] is d[3] at PIN_134
--operation mode is input

d[3] = INPUT();


--d[2] is d[2] at PIN_7
--operation mode is input

d[2] = INPUT();


--d[1] is d[1] at PIN_120
--operation mode is input

d[1] = INPUT();


--d[0] is d[0] at PIN_55
--operation mode is input

d[0] = INPUT();


--ale is ale at PIN_56
--operation mode is output

ale = OUTPUT(B1_current_state.st1);


--start is start at PIN_57
--operation mode is output

start = OUTPUT(B1_current_state.st1);


--oe is oe at PIN_11
--operation mode is output

oe = OUTPUT(B1_oe);


--adda is adda at PIN_32
--operation mode is output

adda = OUTPUT(VCC);


--lock0 is lock0 at PIN_48
--operation mode is output

lock0 = OUTPUT(B1_current_state.st4);


--inclock is inclock at PIN_5
--operation mode is output

inclock = OUTPUT(C1L1);


--address[8] is address[8] at PIN_125
--operation mode is output

address[8] = OUTPUT(C1_cqi[8]);


--address[7] is address[7] at PIN_129
--operation mode is output

address[7] = OUTPUT(C1_cqi[7]);


--address[6] is address[6] at PIN_53
--operation mode is output

address[6] = OUTPUT(C1_cqi[6]);


--address[5] is address[5] at PIN_52
--operation mode is output

address[5] = OUTPUT(C1_cqi[5]);


--address[4] is address[4] at PIN_127
--operation mode is output

address[4] = OUTPUT(C1_cqi[4]);


--address[3] is address[3] at PIN_128
--operation mode is output

address[3] = OUTPUT(C1_cqi[3]);


--address[2] is address[2] at PIN_126
--operation mode is output

address[2] = OUTPUT(C1_cqi[2]);


--address[1] is address[1] at PIN_131
--operation mode is output

address[1] = OUTPUT(C1_cqi[1]);


--address[0] is address[0] at PIN_124
--operation mode is output

address[0] = OUTPUT(C1_cqi[0]);


--joc[7] is joc[7] at PIN_106
--operation mode is output

joc[7] = OUTPUT(J1_safe_q[7]);


--joc[6] is joc[6] at PIN_139
--operation mode is output

joc[6] = OUTPUT(J1_safe_q[6]);


--joc[5] is joc[5] at PIN_3
--operation mode is output

joc[5] = OUTPUT(J1_safe_q[5]);


--joc[4] is joc[4] at PIN_107
--operation mode is output

joc[4] = OUTPUT(J1_safe_q[4]);


--joc[3] is joc[3] at PIN_140
--operation mode is output

joc[3] = OUTPUT(J1_safe_q[3]);


--joc[2] is joc[2] at PIN_1
--operation mode is output

joc[2] = OUTPUT(J1_safe_q[2]);


--joc[1] is joc[1] at PIN_141
--operation mode is output

joc[1] = OUTPUT(J1_safe_q[1]);


--joc[0] is joc[0] at PIN_2
--operation mode is output

joc[0] = OUTPUT(J1_safe_q[0]);


--q[7] is q[7] at PIN_4
--operation mode is output

q[7] = OUTPUT(G1_q_a[7]);


--q[6] is q[6] at PIN_104
--operation mode is output

q[6] = OUTPUT(G1_q_a[6]);


--q[5] is q[5] at PIN_121
--operation mode is output

q[5] = OUTPUT(G1_q_a[5]);


--q[4] is q[4] at PIN_123
--operation mode is output

q[4] = OUTPUT(G1_q_a[4]);


--q[3] is q[3] at PIN_105
--operation mode is output

q[3] = OUTPUT(G1_q_a[3]);


--q[2] is q[2] at PIN_103
--operation mode is output

q[2] = OUTPUT(G1_q_a[2]);


--q[1] is q[1] at PIN_130
--operation mode is output

q[1] = OUTPUT(G1_q_a[1]);


--q[0] is q[0] at PIN_122
--operation mode is output

q[0] = OUTPUT(G1_q_a[0]);