📄 shujucaiji.rpp.talkback.xml
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<location_assigned_by>Fitter</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>oe</name>
<pin__>49</pin__>
<i_o_bank>4</i_o_bank>
<x_coordinate>8</x_coordinate>
<y_coordinate>0</y_coordinate>
<cell_number>0</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>q[0]</name>
<pin__>133</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>8</x_coordinate>
<y_coordinate>14</y_coordinate>
<cell_number>1</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>q[1]</name>
<pin__>127</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>12</x_coordinate>
<y_coordinate>14</y_coordinate>
<cell_number>0</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>q[2]</name>
<pin__>131</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>10</x_coordinate>
<y_coordinate>14</y_coordinate>
<cell_number>1</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>q[3]</name>
<pin__>57</pin__>
<i_o_bank>4</i_o_bank>
<x_coordinate>16</x_coordinate>
<y_coordinate>0</y_coordinate>
<cell_number>0</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>q[4]</name>
<pin__>125</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>16</x_coordinate>
<y_coordinate>14</y_coordinate>
<cell_number>1</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>q[5]</name>
<pin__>129</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>12</x_coordinate>
<y_coordinate>14</y_coordinate>
<cell_number>2</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>q[6]</name>
<pin__>128</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>12</x_coordinate>
<y_coordinate>14</y_coordinate>
<cell_number>1</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>q[7]</name>
<pin__>56</pin__>
<i_o_bank>4</i_o_bank>
<x_coordinate>16</x_coordinate>
<y_coordinate>0</y_coordinate>
<cell_number>1</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>start</name>
<pin__>84</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>27</x_coordinate>
<y_coordinate>5</y_coordinate>
<cell_number>0</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
<load>Unspecified</load>
</row>
</output_pins>
<i_o_bank_usage>
<row>
<i_o_bank>1</i_o_bank>
<usage>7 / 22 ( 32 % )</usage>
<vccio_voltage>3.3V</vccio_voltage>
</row>
<row>
<i_o_bank>2</i_o_bank>
<usage>9 / 28 ( 32 % )</usage>
<vccio_voltage>3.3V</vccio_voltage>
</row>
<row>
<i_o_bank>3</i_o_bank>
<usage>3 / 26 ( 12 % )</usage>
<vccio_voltage>3.3V</vccio_voltage>
</row>
<row>
<i_o_bank>4</i_o_bank>
<usage>7 / 28 ( 25 % )</usage>
<vccio_voltage>3.3V</vccio_voltage>
</row>
</i_o_bank_usage>
<advanced_data___general>
<row>
<name>Status Code</name>
<value>0</value>
</row>
<row>
<name>Desired User Slack</name>
<value>0</value>
</row>
<row>
<name>Fit Attempts</name>
<value>1</value>
</row>
</advanced_data___general>
<advanced_data___placement_preparation>
<row>
<name>Auto Fit Point 1 - Fit Attempt 1</name>
<value>ff</value>
</row>
<row>
<name>Mid Wire Use - Fit Attempt 1</name>
<value>2</value>
</row>
<row>
<name>Mid Slack - Fit Attempt 1</name>
<value>994201</value>
</row>
<row>
<name>Internal Atom Count - Fit Attempt 1</name>
<value>24</value>
</row>
<row>
<name>LE/ALM Count - Fit Attempt 1</name>
<value>24</value>
</row>
<row>
<name>LAB Count - Fit Attempt 1</name>
<value>12</value>
</row>
<row>
<name>Outputs per Lab - Fit Attempt 1</name>
<value>1.833</value>
</row>
<row>
<name>Inputs per LAB - Fit Attempt 1</name>
<value>1.000</value>
</row>
<row>
<name>Global Inputs per LAB - Fit Attempt 1</name>
<value>0.917</value>
</row>
<row>
<name>LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1</name>
<value>0:12</value>
</row>
<row>
<name>LAB Constraint 'ce + sync load' - Fit Attempt 1</name>
<value>0:12</value>
</row>
<row>
<name>LAB Constraint 'non-global controls' - Fit Attempt 1</name>
<value>0:12</value>
</row>
<row>
<name>LAB Constraint 'un-route combination' - Fit Attempt 1</name>
<value>0:12</value>
</row>
<row>
<name>LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1</name>
<value>0:11;1:1</value>
</row>
<row>
<name>LAB Constraint 'un-route with async_clear' - Fit Attempt 1</name>
<value>0:11;1:1</value>
</row>
<row>
<name>LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1</name>
<value>0:12</value>
</row>
<row>
<name>LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1</name>
<value>0:12</value>
</row>
<row>
<name>LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1</name>
<value>0:12</value>
</row>
<row>
<name>LAB Constraint 'global control signals' - Fit Attempt 1</name>
<value>0:2;1:9;2:1</value>
</row>
<row>
<name>LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1</name>
<value>0:2;1:10</value>
</row>
<row>
<name>LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1</name>
<value>0:12</value>
</row>
<row>
<name>LAB Constraint 'aload_aclr pair' - Fit Attempt 1</name>
<value>0:2;1:10</value>
</row>
<row>
<name>LAB Constraint 'sload_sclear pair' - Fit Attempt 1</name>
<value>0:11;1:1</value>
</row>
<row>
<name>LAB Constraint 'invert_a constraint' - Fit Attempt 1</name>
<value>0:11;1:1</value>
</row>
<row>
<name>LAB Constraint 'has placement constraint' - Fit Attempt 1</name>
<value>0:12</value>
</row>
<row>
<name>LEs in Chains - Fit Attempt 1</name>
<value>9</value>
</row>
<row>
<name>LEs in Long Chains - Fit Attempt 1</name>
<value>0</value>
</row>
<row>
<name>LABs with Chains - Fit Attempt 1</name>
<value>1</value>
</row>
<row>
<name>LABs with Multiple Chains - Fit Attempt 1</name>
<value>0</value>
</row>
<row>
<name>Time - Fit Attempt 1</name>
<value>0</value>
</row>
</advanced_data___placement_preparation>
<advanced_data___placement>
<row>
<name>Auto Fit Point 2 - Fit Attempt 1</name>
<value>ff</value>
</row>
<row>
<name>Early Wire Use - Fit Attempt 1</name>
<value>0</value>
</row>
<row>
<name>Early Slack - Fit Attempt 1</name>
<value>993313</value>
</row>
<row>
<name>Auto Fit Point 3 - Fit Attempt 1</name>
<value>ff</value>
</row>
<row>
<name>Mid Wire Use - Fit Attempt 1</name>
<value>1</value>
</row>
<row>
<name>Mid Slack - Fit Attempt 1</name>
<value>993798</value>
</row>
<row>
<name>Auto Fit Point 4 - Fit Attempt 1</name>
<value>ff</value>
</row>
<row>
<name>Late Wire Use - Fit Attempt 1</name>
<value>1</value>
</row>
<row>
<name>Late Slack - Fit Attempt 1</name>
<value>993798</value>
</row>
<row>
<name>Auto Fit Point 5 - Fit Attempt 1</name>
<value>ff</value>
</row>
<row>
<name>Time - Fit Attempt 1</name>
<value>0</value>
</row>
<row>
<name>Time in tsm_dat.dll - Fit Attempt 1</name>
<value>0.047</value>
</row>
<row>
<name>Time in tsm_tan.dll - Fit Attempt 1</name>
<value>0.047</value>
</row>
</advanced_data___placement>
<advanced_data___routing>
<row>
<name>Early Slack - Fit Attempt 1</name>
<value>993102</value>
</row>
<row>
<name>Early Wire Use - Fit Attempt 1</name>
<value>1</value>
</row>
<row>
<name>Peak Regional Wire - Fit Attempt 1</name>
<value>1</value>
</row>
<row>
<name>Mid Slack - Fit Attempt 1</name>
<value>992863</value>
</row>
<row>
<name>Late Slack - Fit Attempt 1</name>
<value>992863</value>
</row>
<row>
<name>Late Slack - Fit Attempt 1</name>
<value>992863</value>
</row>
<row>
<name>Late Wire Use - Fit Attempt 1</name>
<value>1</value>
</row>
<row>
<name>Time - Fit Attempt 1</name>
<value>0</value>
</row>
<row>
<name>Time in tsm_tan.dll - Fit Attempt 1</name>
<value>0.110</value>
</row>
</advanced_data___routing>
</talkback>
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