shujucaiji.rpp.talkback.xml

通过ADC0809对模拟信号进行采样

	<row>
		<option>Ignore translate_off and translate_on Synthesis Directives</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Show Parameter Settings Tables in Synthesis Report</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Ignore Maximum Fan-Out Assignments</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Retiming Meta-Stability Register Sequence Length</option>
		<setting>2</setting>
		<default_value>2</default_value>
	</row>
	<row>
		<option>PowerPlay Power Optimization</option>
		<setting>Normal compilation</setting>
		<default_value>Normal compilation</default_value>
	</row>
	<row>
		<option>HDL message level</option>
		<setting>Level2</setting>
		<default_value>Level2</default_value>
	</row>
</analysis___synthesis_settings>
<assembler_settings>
	<row>
		<option>Use smart compilation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Generate Serial Vector Format File (.svf) for Target Device</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Generate a JEDEC STAPL Format File (.jam) for Target Device</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Generate an uncompressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Generate compressed bitstreams</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Compression mode</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Clock source for configuration device</option>
		<setting>Internal</setting>
		<default_value>Internal</default_value>
	</row>
	<row>
		<option>Clock frequency of the configuration device</option>
		<setting units="MHz">10</setting>
		<default_value units="MHz">10</default_value>
	</row>
	<row>
		<option>Divide clock frequency by</option>
		<setting>1</setting>
		<default_value>1</default_value>
	</row>
	<row>
		<option>JTAG user code for target device</option>
		<setting>Ffffffff</setting>
		<default_value>Ffffffff</default_value>
	</row>
	<row>
		<option>Auto user code</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Use configuration device</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Configuration device</option>
		<setting>Auto</setting>
		<default_value>Auto</default_value>
	</row>
	<row>
		<option>JTAG user code for configuration device</option>
		<setting>Ffffffff</setting>
		<default_value>Ffffffff</default_value>
	</row>
	<row>
		<option>Configuration device auto user code</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Auto-increment JTAG user code for multiple configuration devices</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Generate Tabular Text File (.ttf) For Target Device</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Generate Raw Binary File (.rbf) For Target Device</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Hexadecimal Output File start address</option>
		<setting>0</setting>
		<default_value>0</default_value>
	</row>
	<row>
		<option>Hexadecimal Output File count direction</option>
		<setting>Up</setting>
		<default_value>Up</default_value>
	</row>
	<row>
		<option>Release clears before tri-states</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Auto-restart configuration after error</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
</assembler_settings>
<general_register_statistics>
	<row>
		<statistic>Total registers</statistic>
		<value>22</value>
	</row>
	<row>
		<statistic>Number of registers using Synchronous Clear</statistic>
		<value>0</value>
	</row>
	<row>
		<statistic>Number of registers using Synchronous Load</statistic>
		<value>0</value>
	</row>
	<row>
		<statistic>Number of registers using Asynchronous Clear</statistic>
		<value>9</value>
	</row>
	<row>
		<statistic>Number of registers using Asynchronous Load</statistic>
		<value>0</value>
	</row>
	<row>
		<statistic>Number of registers using Clock Enable</statistic>
		<value>0</value>
	</row>
	<row>
		<statistic>Number of registers using Preset</statistic>
		<value>0</value>
	</row>
</general_register_statistics>
<clock_settings_summary>
	<row>
		<clock_node_name>clk</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
	<row>
		<clock_node_name>wren</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
</clock_settings_summary>
<input_pins>
	<row>
		<name>clk</name>
		<pin__>17</pin__>
		<i_o_bank>1</i_o_bank>
		<x_coordinate>0</x_coordinate>
		<y_coordinate>7</y_coordinate>
		<cell_number>0</cell_number>
		<combinational_fan_out>6</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>yes</global>
		<input_register>no</input_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
	</row>
	<row>
		<name>clr</name>
		<pin__>16</pin__>
		<i_o_bank>1</i_o_bank>
		<x_coordinate>0</x_coordinate>
		<y_coordinate>8</y_coordinate>
		<cell_number>2</cell_number>
		<combinational_fan_out>9</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>yes</global>
		<input_register>no</input_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
	</row>
	<row>
		<name>d[0]</name>
		<pin__>7</pin__>
		<i_o_bank>1</i_o_bank>
		<x_coordinate>0</x_coordinate>
		<y_coordinate>10</y_coordinate>
		<cell_number>0</cell_number>
		<combinational_fan_out>1</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<input_register>no</input_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
	</row>
	<row>
		<name>d[1]</name>
		<pin__>55</pin__>
		<i_o_bank>4</i_o_bank>
		<x_coordinate>16</x_coordinate>
		<y_coordinate>0</y_coordinate>
		<cell_number>2</cell_number>
		<combinational_fan_out>1</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<input_register>no</input_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
	</row>
	<row>
		<name>d[2]</name>
		<pin__>26</pin__>
		<i_o_bank>1</i_o_bank>
		<x_coordinate>0</x_coordinate>
		<y_coordinate>5</y_coordinate>
		<cell_number>1</cell_number>
		<combinational_fan_out>1</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<input_register>no</input_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
	</row>
	<row>
		<name>d[3]</name>
		<pin__>99</pin__>
		<i_o_bank>3</i_o_bank>
		<x_coordinate>27</x_coordinate>
		<y_coordinate>10</y_coordinate>
		<cell_number>1</cell_number>
		<combinational_fan_out>1</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<input_register>no</input_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
	</row>
	<row>
		<name>d[4]</name>
		<pin__>124</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>16</x_coordinate>
		<y_coordinate>14</y_coordinate>
		<cell_number>0</cell_number>
		<combinational_fan_out>1</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<input_register>no</input_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
	</row>
	<row>
		<name>d[5]</name>
		<pin__>122</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>18</x_coordinate>
		<y_coordinate>14</y_coordinate>
		<cell_number>0</cell_number>
		<combinational_fan_out>1</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<input_register>no</input_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
	</row>
	<row>
		<name>d[6]</name>
		<pin__>54</pin__>
		<i_o_bank>4</i_o_bank>
		<x_coordinate>12</x_coordinate>
		<y_coordinate>0</y_coordinate>
		<cell_number>0</cell_number>
		<combinational_fan_out>1</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<input_register>no</input_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
	</row>
	<row>
		<name>d[7]</name>
		<pin__>130</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>10</x_coordinate>
		<y_coordinate>14</y_coordinate>
		<cell_number>0</cell_number>
		<combinational_fan_out>1</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<input_register>no</input_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
	</row>
	<row>
		<name>eoc</name>
		<pin__>48</pin__>
		<i_o_bank>4</i_o_bank>
		<x_coordinate>8</x_coordinate>
		<y_coordinate>0</y_coordinate>
		<cell_number>1</cell_number>
		<combinational_fan_out>2</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<input_register>no</input_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
	</row>
	<row>
		<name>wren</name>
		<pin__>50</pin__>
		<i_o_bank>4</i_o_bank>
		<x_coordinate>10</x_coordinate>
		<y_coordinate>0</y_coordinate>
		<cell_number>1</cell_number>
		<combinational_fan_out>2</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<input_register>no</input_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
	</row>
</input_pins>
<output_pins>
	<row>
		<name>adda</name>
		<pin__>5</pin__>
		<i_o_bank>1</i_o_bank>
		<x_coordinate>0</x_coordinate>
		<y_coordinate>11</y_coordinate>
		<cell_number>0</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
		<load>Unspecified</load>
	</row>
	<row>
		<name>ale</name>
		<pin__>83</pin__>
		<i_o_bank>3</i_o_bank>
		<x_coordinate>27</x_coordinate>
		<y_coordinate>5</y_coordinate>
		<cell_number>1</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>