da.v

6阶FIR+verliog+分布式算法（DA）

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    19:15:12 10/15/07
// Design Name:    谢大钊
// Module Name:    da
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module da(clk, x_in, y); 

  input         clk;
  input  [3:0]  x_in;
  output [6:0]  y;
  reg    [6:0]  y;

  reg  [5:0] x0, x1, x2, x3;
  wire [3:0] y0, y1, y2, y3;
  wire [3:0] y01, y11, y21, y31;
  reg [4:0] y02, y12, y22, y32;
  reg  [5:0] s0, s1;
  reg  [4:0] t0, t1, t2, t3;
  reg [2:0] a0, a1, a2, a3, a4, a5, a6, a7;

  always @(posedge clk)  
  begin : DA 
    integer k;
    for (k=0; k<=4; k=k+1) begin     
       x0[k] <= x0[k+1];
       x1[k] <= x1[k+1];
       x2[k] <= x2[k+1];
       x3[k] <= x3[k+1];
    end
	   a0 <= x0[5:3];
  a1 <= x1[5:3];
  a2 <= x2[5:3];
  a3 <= x3[5:3];
  a4 <= x0[2:0];
  a5 <= x1[2:0];
  a6 <= x2[2:0];
  a7 <= x3[2:0];
    x0[5] <= x_in[0];     
    x1[5] <= x_in[1];    
    x2[5] <= x_in[2];
    x3[5] <= x_in[3];
	 y02 <= y0 + y01;
	 y12 <= y1 + y11;
	 y22 <= y2 + y21;
	 y32 <= y3 + y31;
    //y <= {{3{y02[6]}},y0} + {{2{y12[6]}},y12,1'b0} 
         //+ {y22[6],y22,2'b00} - (y32 << 3);
	 t0 <= y02;
	 t1 <= y12;
	 t2 <= y22;
	 t3 <= y32;
	 s0 <= {t0[4],t0} + (t1 << 1);
	 s1 <= {t2[4],t2} - (t3 << 1);
	 y  <= {{2{s0[5]}},s0} + (s1 << 2);

  end


  dafir LC_Table0 ( .table_in(a0), .table_out(y0));
  dafir LC_Table1 ( .table_in(a1), .table_out(y1));
  dafir LC_Table2 ( .table_in(a2), .table_out(y2));
  dafir LC_Table3 ( .table_in(a3), .table_out(y3));
  dafir1 LC_Table01 ( .table_in(a4), .table_out(y01));
  dafir1 LC_Table11 ( .table_in(a5), .table_out(y11));
  dafir1 LC_Table21 ( .table_in(a6), .table_out(y21));
  dafir1 LC_Table31 ( .table_in(a7), .table_out(y31));

endmodule