📄 spi93c46.tan.rpt
字号:
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------+-----------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------+-----------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 118.23 MHz ( period = 8.458 ns ) ; spi93c46:inst1|current_state.Read19 ; spi93c46:inst1|cs ; clk ; clk ; None ; None ; 3.965 ns ;
; N/A ; 121.33 MHz ( period = 8.242 ns ) ; spi93c46:inst1|current_state.Write19 ; spi93c46:inst1|cs ; clk ; clk ; None ; None ; 3.857 ns ;
; N/A ; 123.24 MHz ( period = 8.114 ns ) ; spi93c46:inst1|current_state.Read7 ; spi93c46:inst1|mo ; clk ; clk ; None ; None ; 3.793 ns ;
; N/A ; 124.84 MHz ( period = 8.010 ns ) ; spi93c46:inst1|current_state.Read6 ; spi93c46:inst1|mo ; clk ; clk ; None ; None ; 3.741 ns ;
; N/A ; 126.23 MHz ( period = 7.922 ns ) ; spi93c46:inst1|current_state.Ewen9 ; spi93c46:inst1|cs ; clk ; clk ; None ; None ; 3.712 ns ;
; N/A ; 130.21 MHz ( period = 7.680 ns ) ; spi93c46:inst1|current_state.Read15 ; spi93c46:inst1|mo ; clk ; clk ; None ; None ; 3.564 ns ;
; N/A ; 131.93 MHz ( period = 7.580 ns ) ; spi93c46:inst1|current_state.Read17 ; spi93c46:inst1|mo ; clk ; clk ; None ; None ; 3.514 ns ;
; N/A ; 133.01 MHz ( period = 7.518 ns ) ; spi93c46:inst1|current_state.Ewen11 ; spi93c46:inst1|cs ; clk ; clk ; None ; None ; 3.497 ns ;
; N/A ; 135.46 MHz ( period = 7.382 ns ) ; spi93c46:inst1|current_state.Write7 ; spi93c46:inst1|mo ; clk ; clk ; None ; None ; 3.427 ns ;
; N/A ; 136.69 MHz ( period = 7.316 ns ) ; spi93c46:inst1|current_state.Idle ; spi93c46:inst1|cs ; clk ; clk ; None ; None ; 3.394 ns ;
; N/A ; 137.70 MHz ( period = 7.262 ns ) ; spi93c46:inst1|current_state.Write5 ; spi93c46:inst1|mo ; clk ; clk ; None ; None ; 3.367 ns ;
; N/A ; 139.47 MHz ( period = 7.170 ns ) ; spi93c46:inst1|current_state.Read19 ; spi93c46:inst1|mo ; clk ; clk ; None ; None ; 3.308 ns ;
; N/A ; 139.70 MHz ( period = 7.158 ns ) ; spi93c46:inst1|current_state.Read8 ; spi93c46:inst1|mo ; clk ; clk ; None ; None ; 3.315 ns ;
; N/A ; 142.65 MHz ( period = 7.010 ns ) ; spi93c46:inst1|current_state.Read0 ; spi93c46:inst1|mo ; clk ; clk ; None ; None ; 3.241 ns ;
; N/A ; 143.43 MHz ( period = 6.972 ns ) ; spi93c46:inst1|current_state.Write15 ; spi93c46:inst1|mo ; clk ; clk ; None ; None ; 3.209 ns ;
; N/A ; 143.80 MHz ( period = 6.954 ns ) ; spi93c46:inst1|current_state.Write19 ; spi93c46:inst1|mo ; clk ; clk ; None ; None ; 3.200 ns ;
; N/A ; 145.90 MHz ( period = 6.854 ns ) ; spi93c46:inst1|current_state.Write9 ; spi93c46:inst1|mo ; clk ; clk ; None ; None ; 3.150 ns ;
; N/A ; 146.20 MHz ( period = 6.840 ns ) ; spi93c46:inst1|current_state.Write2 ; spi93c46:inst1|mo ; clk ; clk ; None ; None ; 3.155 ns ;
; N/A ; 148.85 MHz ( period = 6.718 ns ) ; spi93c46:inst1|current_state.Ewen4 ; spi93c46:inst1|mo ; clk ; clk ; None ; None ; 3.097 ns ;
; N/A ; 149.70 MHz ( period = 6.680 ns ) ; spi93c46:inst1|current_state.Read16 ; spi93c46:inst1|mo ; clk ; clk ; None ; None ; 3.064 ns ;
; N/A ; 150.42 MHz ( period = 6.648 ns ) ; spi93c46:inst1|current_state.Read5 ; spi93c46:inst1|mo ; clk ; clk ; None ; None ; 3.060 ns ;
; N/A ; 150.74 MHz ( period = 6.634 ns ) ; spi93c46:inst1|current_state.Ewen9 ; spi93c46:inst1|mo ; clk ; clk ; None ; None ; 3.055 ns ;
; N/A ; 150.97 MHz ( period = 6.624 ns ) ; spi93c46:inst1|current_state.Write17 ; spi93c46:inst1|mo ; clk ; clk ; None ; None ; 3.035 ns ;
; N/A ; 151.29 MHz ( period = 6.610 ns ) ; spi93c46:inst1|current_state.Read18 ; spi93c46:inst1|cs ; clk ; clk ; None ; None ; 3.042 ns ;
; N/A ; 153.05 MHz ( period = 6.534 ns ) ; spi93c46:inst1|current_state.Read11 ; spi93c46:inst1|mo ; clk ; clk ; None ; None ; 2.991 ns ;
; N/A ; 155.38 MHz ( period = 6.436 ns ) ; spi93c46:inst1|current_state.Read12 ; spi93c46:inst1|mo ; clk ; clk ; None ; None ; 2.942 ns ;
; N/A ; 156.20 MHz ( period = 6.402 ns ) ; spi93c46:inst1|current_state.Read1 ; spi93c46:inst1|mo ; clk ; clk ; None ; None ; 2.941 ns ;
; N/A ; 156.20 MHz ( period = 6.402 ns ) ; spi93c46:inst1|current_state.Write4 ; spi93c46:inst1|mo ; clk ; clk ; None ; None ; 2.937 ns ;
; N/A ; 158.28 MHz ( period = 6.318 ns ) ; spi93c46:inst1|current_state.Ewen0 ; spi93c46:inst1|mo ; clk ; clk ; None ; None ; 2.895 ns ;
; N/A ; 160.51 MHz ( period = 6.230 ns ) ; spi93c46:inst1|current_state.Ewen11 ; spi93c46:inst1|mo ; clk ; clk ; None ; None ; 2.840 ns ;
; N/A ; 161.50 MHz ( period = 6.192 ns ) ; spi93c46:inst1|current_state.Read14 ; spi93c46:inst1|mo ; clk ; clk ; None ; None ; 2.820 ns ;
; N/A ; 165.89 MHz ( period = 6.028 ns ) ; spi93c46:inst1|current_state.Idle ; spi93c46:inst1|mo ; clk ; clk ; None ; None ; 2.737 ns ;
; N/A ; 166.39 MHz ( period = 6.010 ns ) ; spi93c46:inst1|current_state.Write8 ; spi93c46:inst1|mo ; clk ; clk ; None ; None ; 2.728 ns ;
; N/A ; 166.67 MHz ( period = 6.000 ns ) ; spi93c46:inst1|current_state.Read0 ; spi93c46:inst1|cs ; clk ; clk ; None ; None ; 2.749 ns ;
; N/A ; 169.09 MHz ( period = 5.914 ns ) ; spi93c46:inst1|current_state.Write6 ; spi93c46:inst1|mo ; clk ; clk ; None ; None ; 2.693 ns ;
; N/A ; 171.94 MHz ( period = 5.816 ns ) ; spi93c46:inst1|current_state.Write0 ; spi93c46:inst1|mo ; clk ; clk ; None ; None ; 2.644 ns ;
; N/A ; 178.13 MHz ( period = 5.614 ns ) ; spi93c46:inst1|current_state.Write16 ; spi93c46:inst1|mo ; clk ; clk ; None ; None ; 2.530 ns ;
; N/A ; 181.55 MHz ( period = 5.508 ns ) ; spi93c46:inst1|current_state.Write14 ; spi93c46:inst1|mo ; clk ; clk ; None ; None ; 2.477 ns ;
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