control_led.vhd

来自「介绍了如何用vhdl语言实现处理器的spi接口」· VHDL 代码 · 共 66 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity control_led is
port ( reset_n : in std_logic;
       clk     : in std_logic;
       datain  : in std_logic_vector(19 downto 0);
       dataout : out std_logic;
       dclkout : out std_logic;
       rclkout : out std_logic
     );
end control_led;

architecture rtl of control_led is
signal data_out : std_logic;
signal counter  : integer range 0 to 20 := 20;
signal flag     : std_logic;
begin 
---------------------------------out--------------------------------
dataout <= data_out;
dclkout <= not clk when flag = '0' else
            '0' when flag = '1';
           
rclkout <= not clk  when flag = '1' else
            '0' when flag = '0';
--------------------------------------------------------------------
process ( reset_n,clk)
begin 
  if reset_n = '0' then 
    counter <= 20;
  elsif clk'event and clk = '1' then
    if counter = 0 then
       counter <= 20;
    else
       counter <= counter - 1 ;
    end if;
  end if;
end process;

process (reset_n,clk)
begin
  if reset_n = '0' then 
     data_out <= '0';
  elsif clk'event and clk = '1' then 
     if counter /= 0 then
      data_out <= datain(counter-1);
     end if;
  end if;
end process;

process (reset_n,clk)
begin
  if reset_n = '0' then
     flag <= '0';
  elsif clk'event and clk = '1' then
     if counter = 0 then
       flag <= '1';
     else
       flag <= '0';
     end if;
  end if;
end process;

end rtl;