mo.v

来自「介绍了如何用vhdl语言实现处理器的spi接口」· Verilog 代码 · 共 19 行

module mo(clk,en,pi,so);

input clk,en;
input [7:0] pi;
output so;

reg so;
integer count;

always @(posedge clk)
if(en)
	count = 0;
else
	if(count < 8)
		begin
		so <= pi[count];
		count <= count+1;				
		end
endmodule