mi.v

来自「介绍了如何用vhdl语言实现处理器的spi接口」· Verilog 代码 · 共 19 行

module mi(clk,en,si,po);

input clk,en;
input si;
output [7:0] po;

reg [7:0] po;
integer count;

always @(posedge clk)
if(en)
	count = 0;
else
	if(count < 8)
		begin
		po[count] <= si;
		count = count+1;				
		end
endmodule