spi93c46.v

介绍了如何用vhdl语言实现处理器的spi接口

module spi93c46 (rst, clk, sck, mo, mi, cs, led, write, read);
input rst, clk, mi, write, read;
output sck, cs, mo;
output [7:0] led;

reg [7:0] led;
reg cs;
reg mo;

assign sck = clk;


//状态机
parameter 	Idle = 32'd1,
 
			Ewen0=32'd10, Ewen1=32'd11, Ewen2=32'd12, Ewen3=32'd13, Ewen4=32'd14, 
			Ewen5=32'd15, Ewen6=32'd16,Ewen7=32'd17, Ewen8=32'd18, Ewen9=32'd19,
			Ewen10=32'd110, Ewen11=32'd111,
			
			Write0=32'd20,Write1=32'd21,Write2=32'd22,Write3=32'd23,Write4=32'd24,
			Write5=32'd25,Write6=32'd26,Write7=32'd27,Write8=32'd28,Write9=32'd29,
			Write10=32'd120,Write11=32'd121,Write12=32'd122,Write13=32'd123,Write14=32'd124,
			Write15=32'd125,Write16=32'd126,Write17=32'd127,Write18=32'd128,Write19=32'd129,
		
			
			Read0=32'd30, Read1=32'd31, Read2=32'd32, Read3=32'd33, Read4=32'd34, 
			Read5=32'd35, Read6=32'd36, Read7=32'd37, Read8=32'd38, Read9=32'd39,
			Read10=32'd130, Read11=32'd131, Read12=32'd132, Read13=32'd133, Read14=32'd134, 
			Read15=32'd135, Read16=32'd136, Read17=32'd137, Read18=32'd138, Read19=32'd139;
			    
reg[31:0] current_state;
reg[31:0] next_state;

//第一个进程
always @(posedge clk ) 
if(rst)
   current_state <= Idle;
else
   current_state <= next_state;//注意，使用的是非阻塞赋值


//第二个进程，组合逻辑always模块，描述状态转移条件判断
always @ (current_state or write or read)   //电平触发
begin
    next_state = Idle; //要初始化，使得系统复位后能进入正确的状态
    case(current_state)
    Idle: 
       	if(write)
			next_state = Ewen0;
		else if(read)
			next_state = Read0;
		else  
			next_state = Idle; //阻塞赋值
	
	Ewen0:
		next_state = Ewen1;
	Ewen1:
		next_state = Ewen2;
	Ewen2:
		next_state = Ewen3;
	Ewen3:
		next_state = Ewen4;
	Ewen4:
		next_state = Ewen5;
	Ewen5:
		next_state = Ewen6;
	Ewen6:
		next_state = Ewen7;
	Ewen7:
		next_state = Ewen8;
	Ewen8:
		next_state = Ewen9;
	Ewen9:
		next_state = Ewen10;
	Ewen10:
		next_state = Ewen11;
	Ewen11:
		next_state = Write0;
	
	Write0:
		next_state = Write1;
	Write1:
		next_state = Write2;
	Write2:
		next_state = Write3;
	Write3:
		next_state = Write4;
	Write4:
		next_state = Write5;
	Write5:
		next_state = Write6;
	Write6:
		next_state = Write7;
	Write7:
		next_state = Write8;
	Write8:
		next_state = Write9;
	Write9:
		next_state = Write10;
	Write10:
		next_state = Write11;
	Write11:
		next_state = Write12;
	Write12:
		next_state = Write13;
	Write13:
		next_state = Write14;
	Write14:
		next_state = Write15;
	Write15:
		next_state = Write16;
	Write16:
		next_state = Write17;
	Write17:
		next_state = Write18;
	Write18:
		next_state = Write19;
	Write19:
		next_state = Idle;


	Read0:
		next_state = Read1;
	Read1:
		next_state = Read2;
	Read2:
		next_state = Read3;
	Read3:
		next_state = Read4;
	Read4:
		next_state = Read5;
	Read5:
		next_state = Read6;
	Read6:
		next_state = Read7;
	Read7:
		next_state = Read8;
	Read8:
		next_state = Read9;
	Read9:
		next_state = Read10;
	Read10:
		next_state = Read11;
	Read11:
		next_state = Read12;
	Read12:
		next_state = Read13;
	Read13:
		next_state = Read14;
	Read14:
		next_state = Read15;
	Read15:
		next_state = Read16;
	Read16:
		next_state = Read17;
	Read17:
		next_state = Read18;
	Read18:
		next_state = Read19;
	Read19:
		next_state = Idle;
	
    endcase
end 


//第三个进程，同步时序always模块，格式化描述次态寄存器输出
always @ (negedge clk)
	case(next_state)
    Idle: 
       	cs <= 0;	
	Ewen0:
		cs <= 0;
	Ewen1:
		begin
		cs <= 1;
		mo <= 1;
		end
	Ewen2:
		mo <= 0;
	Ewen3:
		mo <= 0;
	Ewen4:
		mo <= 1;
	Ewen5:
		mo <= 1;//以下四个为无用信号
	Ewen6:
		mo <= 0;
	Ewen7:
		mo <= 0;
	Ewen8:
		mo <= 0;
	Ewen9:
		mo <= 0;
	Ewen10:
		cs <= 0;
	Ewen11:
		cs <= 0;
	
	Write0:
		cs <= 0;
	Write1:
		begin
		cs <= 1;
		mo <= 1;
		end
	Write2:
		mo <= 0;
	Write3:
		mo <= 1;//101+add(7bit)
	Write4:
		mo <= 0;
	Write5:
		mo <= 1;
	Write6:
		mo <= 1;
	Write7:
		mo <= 1;
	Write8:
		mo <= 1;
	Write9:
		mo <= 1;
	Write10:
		mo <= 1;
	Write11:	//data 8bit
		mo <= 0;
	Write12:
		mo <= 0;
	Write13:
		mo <= 0;
	Write14:
		mo <= 0;
	Write15:
		mo <= 1;
	Write16:
		mo <= 1;
	Write17:
		mo <= 1;
	Write18:
		mo <= 1;
	Write19:
		begin
		mo <= 0;
		cs <= 0;
		end


	Read0:
		cs <= 0;
	Read1://110+add(7bit)
		begin
		cs <= 1;
		mo <= 1;
		end
	Read2:
		mo <= 1;
	Read3:
		mo <= 0;//110
	Read4:
		mo <= 0;
	Read5:
		mo <= 1;
	Read6:
		mo <= 1;
	Read7:
		mo <= 1;
	Read8:
		mo <= 1;
	Read9:
		mo <= 1;
	Read10:
		mo <= 1;
	Read11:
		begin
		mo <= 0;
		led[7] <= mi;
		end
	Read12:
		led[7] <= mi;
	Read13:
		led[6] <= mi;
	Read14:
		led[5] <= mi;
	Read15:
		led[4] <= mi;
	Read16:
		led[3] <= mi;
	Read17:
		led[2] <= mi;
	Read18:
		led[1] <= mi;
	Read19:
		begin
		led[0] <= mi;
		cs <= 0;
		end
	endcase



endmodule