three_spi.vhd

来自「介绍了如何用vhdl语言实现处理器的spi接口」· VHDL 代码 · 共 45 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

entity sig_new is
port(
      SCK,SDA,CS : in std_logic;
            data : out std_logic_vector(11 downto 0);
        counter2 : buffer std_logic_vector(3 downto 0);
        counter1 : out std_logic_vector(3 downto 0)
);
end entity;

architecture behavior of sig_new is
signal datatemp : std_logic_vector(11 downto 0);
signal counter  : std_logic_vector(3 downto 0);
begin

P1: process(SCK,CS)
begin
	if SCK'event and SCK = '1' then
		if CS = '0' then
			if counter < "1100" then
				counter <= counter + 1;
				counter2 <= counter;
				for i in 0 to 10 loop      -- the methord of shifting
					datatemp(11-i) <= datatemp(10-i);
				end loop;
				datatemp(0) <= SDA;
			end if;
		end if;
	end if;

	if CS = '1' and CS'LAST_VALUE = '0' then
		if counter2 = "1011" then
			data <= datatemp;
		end if;
		counter <= "0000";
	end if;
end process;

counter1 <= counter;

end architecture;