pro3.map.qmsg

介绍了如何用vhdl语言实现处理器的spi接口

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version " "Info: Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 10 13:49:51 2008 " "Info: Processing started: Thu Jan 10 13:49:51 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off pro3 -c pro3 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off pro3 -c pro3" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "D:/TDdownload2/SPI接口VHDL的基本設計/Vhdl1.vhd " "Warning: Can't analyze file -- file D:/TDdownload2/SPI接口VHDL的基本設計/Vhdl1.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "D:/TDdownload2/SPI接口VHDL的基本設計/Vhdl2.vhd " "Warning: Can't analyze file -- file D:/TDdownload2/SPI接口VHDL的基本設計/Vhdl2.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.vhd " "Warning: Can't analyze file -- file D:/TDdownload2/SPI接口VHDL的基本設計/pro3.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sipo.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file sipo.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sipo-a " "Info: Found design unit 1: sipo-a" {  } { { "sipo.vhd" "" { Text "D:/TDdownload2/SPI接口VHDL的基本設計/sipo.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sipo " "Info: Found entity 1: sipo" {  } { { "sipo.vhd" "" { Text "D:/TDdownload2/SPI接口VHDL的基本設計/sipo.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sopi.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file sopi.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sopi-a " "Info: Found design unit 1: sopi-a" {  } { { "sopi.vhd" "" { Text "D:/TDdownload2/SPI接口VHDL的基本設計/sopi.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sopi " "Info: Found entity 1: sopi" {  } { { "sopi.vhd" "" { Text "D:/TDdownload2/SPI接口VHDL的基本設計/sopi.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.gdf " "Warning: Can't analyze file -- file D:/TDdownload2/SPI接口VHDL的基本設計/pro3.gdf is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pro3.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file pro3.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 pro3 " "Info: Found entity 1: pro3" {  } { { "pro3.bdf" "" { Schematic "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pro4.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file pro4.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 pro4 " "Info: Found entity 1: pro4" {  } { { "pro4.bdf" "" { Schematic "D:/TDdownload2/SPI接口VHDL的基本設計/pro4.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pro5.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file pro5.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 pro5 " "Info: Found entity 1: pro5" {  } { { "pro5.bdf" "" { Schematic "D:/TDdownload2/SPI接口VHDL的基本設計/pro5.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pro6.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file pro6.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 pro6 " "Info: Found entity 1: pro6" {  } { { "pro6.bdf" "" { Schematic "D:/TDdownload2/SPI接口VHDL的基本設計/pro6.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "pro5 " "Info: Elaborating entity \"pro5\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sopi sopi:inst " "Info: Elaborating entity \"sopi\" for hierarchy \"sopi:inst\"" {  } { { "pro5.bdf" "inst" { Schematic "D:/TDdownload2/SPI接口VHDL的基本設計/pro5.bdf" { { 248 264 424 344 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "data_in sopi.vhd(16) " "Warning (10492): VHDL Process Statement warning at sopi.vhd(16): signal \"data_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "sopi.vhd" "" { Text "D:/TDdownload2/SPI接口VHDL的基本設計/sopi.vhd" 16 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "q sopi.vhd(13) " "Warning (10631): VHDL Process Statement warning at sopi.vhd(13): signal or variable \"q\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"q\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "sopi.vhd" "" { Text "D:/TDdownload2/SPI接口VHDL的基本設計/sopi.vhd" 13 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: signal or variable \"%1!s!\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sipo sipo:inst1 " "Info: Elaborating entity \"sipo\" for hierarchy \"sipo:inst1\"" {  } { { "pro5.bdf" "inst1" { Schematic "D:/TDdownload2/SPI接口VHDL的基本設計/pro5.bdf" { { 72 336 464 168 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR_HDR" "" "Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" { { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "inst7 " "Warning: Converting TRI node \"inst7\" that feeds logic to a wire" {  } { { "pro5.bdf" "" { Schematic "D:/TDdownload2/SPI接口VHDL的基本設計/pro5.bdf" { { 88 232 280 120 "inst7" "" } } } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0}  } {  } 0 0 "Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "38 " "Info: Implemented 38 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "12 " "Info: Implemented 12 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "9 " "Info: Implemented 9 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "17 " "Info: Implemented 17 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 8 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 10 13:49:56 2008 " "Info: Processing ended: Thu Jan 10 13:49:56 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}