pro3.fit.qmsg

介绍了如何用vhdl语言实现处理器的spi接口

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version " "Info: Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 10 13:49:59 2008 " "Info: Processing started: Thu Jan 10 13:49:59 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off pro3 -c pro3 " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off pro3 -c pro3" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "pro3 EP1C6Q240C8 " "Info: Selected device EP1C6Q240C8 for design \"pro3\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12Q240C8 " "Info: Device EP1C12Q240C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "17 21 " "Info: No exact pin location assignment(s) for 17 pins of 21 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "d_out\[7\] " "Info: Pin d_out\[7\] not assigned to an exact location on the device" {  } { { "pro5.bdf" "" { Schematic "D:/TDdownload2/SPI接口VHDL的基本設計/pro5.bdf" { { 96 496 672 112 "d_out\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "d_out\[7\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "D:/TDdownload2/SPI接口VHDL的基本設計/db/pro3.quartus_db" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/" "" "" { d_out[7] } "NODE_NAME" } "" } } { "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" "" { d_out[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "d_out\[6\] " "Info: Pin d_out\[6\] not assigned to an exact location on the device" {  } { { "pro5.bdf" "" { Schematic "D:/TDdownload2/SPI接口VHDL的基本設計/pro5.bdf" { { 96 496 672 112 "d_out\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "d_out\[6\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "D:/TDdownload2/SPI接口VHDL的基本設計/db/pro3.quartus_db" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/" "" "" { d_out[6] } "NODE_NAME" } "" } } { "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" "" { d_out[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "d_out\[5\] " "Info: Pin d_out\[5\] not assigned to an exact location on the device" {  } { { "pro5.bdf" "" { Schematic "D:/TDdownload2/SPI接口VHDL的基本設計/pro5.bdf" { { 96 496 672 112 "d_out\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "d_out\[5\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "D:/TDdownload2/SPI接口VHDL的基本設計/db/pro3.quartus_db" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/" "" "" { d_out[5] } "NODE_NAME" } "" } } { "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" "" { d_out[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "d_out\[4\] " "Info: Pin d_out\[4\] not assigned to an exact location on the device" {  } { { "pro5.bdf" "" { Schematic "D:/TDdownload2/SPI接口VHDL的基本設計/pro5.bdf" { { 96 496 672 112 "d_out\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "d_out\[4\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "D:/TDdownload2/SPI接口VHDL的基本設計/db/pro3.quartus_db" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/" "" "" { d_out[4] } "NODE_NAME" } "" } } { "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" "" { d_out[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "d_out\[3\] " "Info: Pin d_out\[3\] not assigned to an exact location on the device" {  } { { "pro5.bdf" "" { Schematic "D:/TDdownload2/SPI接口VHDL的基本設計/pro5.bdf" { { 96 496 672 112 "d_out\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "d_out\[3\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "D:/TDdownload2/SPI接口VHDL的基本設計/db/pro3.quartus_db" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/" "" "" { d_out[3] } "NODE_NAME" } "" } } { "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" "" { d_out[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "d_out\[2\] " "Info: Pin d_out\[2\] not assigned to an exact location on the device" {  } { { "pro5.bdf" "" { Schematic "D:/TDdownload2/SPI接口VHDL的基本設計/pro5.bdf" { { 96 496 672 112 "d_out\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "d_out\[2\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "D:/TDdownload2/SPI接口VHDL的基本設計/db/pro3.quartus_db" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/" "" "" { d_out[2] } "NODE_NAME" } "" } } { "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" "" { d_out[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "d_out\[1\] " "Info: Pin d_out\[1\] not assigned to an exact location on the device" {  } { { "pro5.bdf" "" { Schematic "D:/TDdownload2/SPI接口VHDL的基本設計/pro5.bdf" { { 96 496 672 112 "d_out\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "d_out\[1\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "D:/TDdownload2/SPI接口VHDL的基本設計/db/pro3.quartus_db" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/" "" "" { d_out[1] } "NODE_NAME" } "" } } { "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" "" { d_out[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "d_out\[0\] " "Info: Pin d_out\[0\] not assigned to an exact location on the device" {  } { { "pro5.bdf" "" { Schematic "D:/TDdownload2/SPI接口VHDL的基本設計/pro5.bdf" { { 96 496 672 112 "d_out\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "d_out\[0\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "D:/TDdownload2/SPI接口VHDL的基本設計/db/pro3.quartus_db" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/" "" "" { d_out[0] } "NODE_NAME" } "" } } { "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" "" { d_out[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "load " "Info: Pin load not assigned to an exact location on the device" {  } { { "pro5.bdf" "" { Schematic "D:/TDdownload2/SPI接口VHDL的基本設計/pro5.bdf" { { 288 48 216 304 "load" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "load" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "D:/TDdownload2/SPI接口VHDL的基本設計/db/pro3.quartus_db" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/" "" "" { load } "NODE_NAME" } "" } } { "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" "" { load } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[7\] " "Info: Pin data_in\[7\] not assigned to an exact location on the device" {  } { { "pro5.bdf" "" { Schematic "D:/TDdownload2/SPI接口VHDL的基本設計/pro5.bdf" { { 304 48 216 320 "data_in\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_in\[7\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "D:/TDdownload2/SPI接口VHDL的基本設計/db/pro3.quartus_db" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/" "" "" { data_in[7] } "NODE_NAME" } "" } } { "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" "" { data_in[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[6\] " "Info: Pin data_in\[6\] not assigned to an exact location on the device" {  } { { "pro5.bdf" "" { Schematic "D:/TDdownload2/SPI接口VHDL的基本設計/pro5.bdf" { { 304 48 216 320 "data_in\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_in\[6\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "D:/TDdownload2/SPI接口VHDL的基本設計/db/pro3.quartus_db" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/" "" "" { data_in[6] } "NODE_NAME" } "" } } { "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" "" { data_in[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[5\] " "Info: Pin data_in\[5\] not assigned to an exact location on the device" {  } { { "pro5.bdf" "" { Schematic "D:/TDdownload2/SPI接口VHDL的基本設計/pro5.bdf" { { 304 48 216 320 "data_in\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_in\[5\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "D:/TDdownload2/SPI接口VHDL的基本設計/db/pro3.quartus_db" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/" "" "" { data_in[5] } "NODE_NAME" } "" } } { "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" "" { data_in[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[4\] " "Info: Pin data_in\[4\] not assigned to an exact location on the device" {  } { { "pro5.bdf" "" { Schematic "D:/TDdownload2/SPI接口VHDL的基本設計/pro5.bdf" { { 304 48 216 320 "data_in\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_in\[4\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "D:/TDdownload2/SPI接口VHDL的基本設計/db/pro3.quartus_db" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/" "" "" { data_in[4] } "NODE_NAME" } "" } } { "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" "" { data_in[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[3\] " "Info: Pin data_in\[3\] not assigned to an exact location on the device" {  } { { "pro5.bdf" "" { Schematic "D:/TDdownload2/SPI接口VHDL的基本設計/pro5.bdf" { { 304 48 216 320 "data_in\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_in\[3\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "D:/TDdownload2/SPI接口VHDL的基本設計/db/pro3.quartus_db" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/" "" "" { data_in[3] } "NODE_NAME" } "" } } { "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" "" { data_in[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[2\] " "Info: Pin data_in\[2\] not assigned to an exact location on the device" {  } { { "pro5.bdf" "" { Schematic "D:/TDdownload2/SPI接口VHDL的基本設計/pro5.bdf" { { 304 48 216 320 "data_in\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_in\[2\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "D:/TDdownload2/SPI接口VHDL的基本設計/db/pro3.quartus_db" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/" "" "" { data_in[2] } "NODE_NAME" } "" } } { "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" "" { data_in[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[1\] " "Info: Pin data_in\[1\] not assigned to an exact location on the device" {  } { { "pro5.bdf" "" { Schematic "D:/TDdownload2/SPI接口VHDL的基本設計/pro5.bdf" { { 304 48 216 320 "data_in\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_in\[1\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "D:/TDdownload2/SPI接口VHDL的基本設計/db/pro3.quartus_db" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/" "" "" { data_in[1] } "NODE_NAME" } "" } } { "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" "" { data_in[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[0\] " "Info: Pin data_in\[0\] not assigned to an exact location on the device" {  } { { "pro5.bdf" "" { Schematic "D:/TDdownload2/SPI接口VHDL的基本設計/pro5.bdf" { { 304 48 216 320 "data_in\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_in\[0\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "D:/TDdownload2/SPI接口VHDL的基本設計/db/pro3.quartus_db" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/" "" "" { data_in[0] } "NODE_NAME" } "" } } { "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" "" { data_in[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Performing register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Completed register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock " "Info: Automatically promoted signal \"clk\" to use Global clock" {  } { { "pro5.bdf" "" { Schematic "D:/TDdownload2/SPI接口VHDL的基本設計/pro5.bdf" { { 184 48 216 200 "clk" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "clk " "Info: Pin \"clk\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "pro5.bdf" "" { Schematic "D:/TDdownload2/SPI接口VHDL的基本設計/pro5.bdf" { { 184 48 216 200 "clk" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pro3" "UNKNOWN" "V1" "D:/TDdownload2/SPI接口VHDL的基本設計/db/pro3.quartus_db" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/" "" "" { clk } "NODE_NAME" } "" } } { "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" { Floorplan "D:/TDdownload2/SPI接口VHDL的基本設計/pro3.fld" "" "" { clk } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0}