pro3.flow.rpt

介绍了如何用vhdl语言实现处理器的spi接口

Flow report for pro3
Thu Jan 10 13:50:14 2008
Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Elapsed Time
  5. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------+
; Flow Summary                                                            ;
+-------------------------+-----------------------------------------------+
; Flow Status             ; Successful - Thu Jan 10 13:50:14 2008         ;
; Quartus II Version      ; 5.1 Build 213 01/19/2006 SP 1 SJ Full Version ;
; Revision Name           ; pro3                                          ;
; Top-level Entity Name   ; pro5                                          ;
; Family                  ; Cyclone                                       ;
; Device                  ; EP1C6Q240C8                                   ;
; Timing Models           ; Final                                         ;
; Met timing requirements ; Yes                                           ;
; Total logic elements    ; 16 / 5,980 ( < 1 % )                          ;
; Total pins              ; 21 / 185 ( 11 % )                             ;
; Total virtual pins      ; 0                                             ;
; Total memory bits       ; 0 / 92,160 ( 0 % )                            ;
; Total PLLs              ; 0 / 2 ( 0 % )                                 ;
+-------------------------+-----------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 01/10/2008 13:49:51 ;
; Main task         ; Compilation         ;
; Revision Name     ; pro3                ;
+-------------------+---------------------+


+-------------------------------------+
; Flow Elapsed Time                   ;
+----------------------+--------------+
; Module Name          ; Elapsed Time ;
+----------------------+--------------+
; Analysis & Synthesis ; 00:00:07     ;
; Fitter               ; 00:00:08     ;
; Assembler            ; 00:00:02     ;
; Timing Analyzer      ; 00:00:01     ;
; Total                ; 00:00:18     ;
+----------------------+--------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off pro3 -c pro3
quartus_fit --read_settings_files=off --write_settings_files=off pro3 -c pro3
quartus_asm --read_settings_files=off --write_settings_files=off pro3 -c pro3
quartus_tan --read_settings_files=off --write_settings_files=off pro3 -c pro3 --timing_analysis_only