📄 oc8051_b_register.v
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////////////////////////////////////////////////////////////////////////// //////// 8051 cores b register //////// //////// This file is part of the 8051 cores project //////// http://www.opencores.org/cores/8051/ //////// //////// Description //////// b register for 8051 core //////// //////// To Do: //////// Nothing //////// //////// Author(s): //////// - Simon Teran, simont@opencores.org //////// ////////////////////////////////////////////////////////////////////////////// //////// Copyright (C) 2000 Authors and OPENCORES.ORG //////// //////// This source file may be used and distributed without //////// restriction provided that this copyright statement is not //////// removed from the file and that any derivative work contains //////// the original copyright notice and the associated disclaimer. //////// //////// This source file is free software; you can redistribute it //////// and/or modify it under the terms of the GNU Lesser General //////// Public License as published by the Free Software Foundation; //////// either version 2.1 of the License, or (at your option) any //////// later version. //////// //////// This source is distributed in the hope that it will be //////// useful, but WITHOUT ANY WARRANTY; without even the implied //////// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //////// PURPOSE. See the GNU Lesser General Public License for more //////// details. //////// //////// You should have received a copy of the GNU Lesser General //////// Public License along with this source; if not, download it //////// from http://www.opencores.org/lgpl.shtml //////// ////////////////////////////////////////////////////////////////////////////// CVS Revision History//// $Log: oc8051_b_register.v,v $// Revision 1.9 2003/04/09 16:24:03 simont// change wr_sft to 2 bit wire.//// Revision 1.8 2003/04/07 14:58:02 simont// change sfr's interface.//// Revision 1.7 2003/01/13 14:14:40 simont// replace some modules//// Revision 1.6 2002/09/30 17:33:59 simont// prepared header////// synopsys translate_off`include "oc8051_timescale.v"// synopsys translate_on`include "oc8051_defines.v"module oc8051_b_register (clk, rst, bit_in, data_in, wr, wr_bit, wr_addr, data_out);input clk, rst, wr, wr_bit, bit_in;input [7:0] wr_addr, data_in;output [7:0] data_out;reg [7:0] data_out;////writing to b//must check if write high and correct addressalways @(posedge clk or posedge rst)begin if (rst) data_out <= #1 `OC8051_RST_B; else if (wr) begin if (!wr_bit) begin if (wr_addr==`OC8051_SFR_B) data_out <= #1 data_in; end else begin if (wr_addr[7:3]==`OC8051_SFR_B_B) data_out[wr_addr[2:0]] <= #1 bit_in; end endendendmodule
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