oc8051_rom.v

verilog code,about oc8051

    7'd83: begin
      data1 <= #1 int_data83;
      data2 <= #1 int_data84;
      data3 <= #1 int_data85;
	end
    7'd84: begin
      data1 <= #1 int_data84;
      data2 <= #1 int_data85;
      data3 <= #1 int_data86;
	end
    7'd85: begin
      data1 <= #1 int_data85;
      data2 <= #1 int_data86;
      data3 <= #1 int_data87;
	end
    7'd86: begin
      data1 <= #1 int_data86;
      data2 <= #1 int_data87;
      data3 <= #1 int_data88;
	end
    7'd87: begin
      data1 <= #1 int_data87;
      data2 <= #1 int_data88;
      data3 <= #1 int_data89;
	end
    7'd88: begin
      data1 <= #1 int_data88;
      data2 <= #1 int_data89;
      data3 <= #1 int_data90;
	end
    7'd89: begin
      data1 <= #1 int_data89;
      data2 <= #1 int_data90;
      data3 <= #1 int_data91;
	end
    7'd90: begin
      data1 <= #1 int_data90;
      data2 <= #1 int_data91;
      data3 <= #1 int_data92;
	end
    7'd91: begin
      data1 <= #1 int_data91;
      data2 <= #1 int_data92;
      data3 <= #1 int_data93;
	end
    7'd92: begin
      data1 <= #1 int_data92;
      data2 <= #1 int_data93;
      data3 <= #1 int_data94;
	end
    7'd93: begin
      data1 <= #1 int_data93;
      data2 <= #1 int_data94;
      data3 <= #1 int_data95;
	end
    7'd94: begin
      data1 <= #1 int_data94;
      data2 <= #1 int_data95;
      data3 <= #1 int_data96;
	end
    7'd95: begin
      data1 <= #1 int_data95;
      data2 <= #1 int_data96;
      data3 <= #1 int_data97;
	end
    7'd96: begin
      data1 <= #1 int_data96;
      data2 <= #1 int_data97;
      data3 <= #1 int_data98;
	end
    7'd97: begin
      data1 <= #1 int_data97;
      data2 <= #1 int_data98;
      data3 <= #1 int_data99;
	end
    7'd98: begin
      data1 <= #1 int_data98;
      data2 <= #1 int_data99;
      data3 <= #1 int_data100;
	end
    7'd99: begin
      data1 <= #1 int_data99;
      data2 <= #1 int_data100;
      data3 <= #1 int_data101;
	end
    7'd100: begin
      data1 <= #1 int_data100;
      data2 <= #1 int_data101;
      data3 <= #1 int_data102;
	end
    7'd101: begin
      data1 <= #1 int_data101;
      data2 <= #1 int_data102;
      data3 <= #1 int_data103;
	end
    7'd102: begin
      data1 <= #1 int_data102;
      data2 <= #1 int_data103;
      data3 <= #1 int_data104;
	end
    7'd103: begin
      data1 <= #1 int_data103;
      data2 <= #1 int_data104;
      data3 <= #1 int_data105;
	end
    7'd104: begin
      data1 <= #1 int_data104;
      data2 <= #1 int_data105;
      data3 <= #1 int_data106;
	end
    7'd105: begin
      data1 <= #1 int_data105;
      data2 <= #1 int_data106;
      data3 <= #1 int_data107;
	end
    7'd106: begin
      data1 <= #1 int_data106;
      data2 <= #1 int_data107;
      data3 <= #1 int_data108;
	end
    7'd107: begin
      data1 <= #1 int_data107;
      data2 <= #1 int_data108;
      data3 <= #1 int_data109;
	end
    7'd108: begin
      data1 <= #1 int_data108;
      data2 <= #1 int_data109;
      data3 <= #1 int_data110;
	end
    7'd109: begin
      data1 <= #1 int_data109;
      data2 <= #1 int_data110;
      data3 <= #1 int_data111;
	end
    7'd110: begin
      data1 <= #1 int_data110;
      data2 <= #1 int_data111;
      data3 <= #1 int_data112;
	end
    7'd111: begin
      data1 <= #1 int_data111;
      data2 <= #1 int_data112;
      data3 <= #1 int_data113;
	end
    7'd112: begin
      data1 <= #1 int_data112;
      data2 <= #1 int_data113;
      data3 <= #1 int_data114;
	end
    7'd113: begin
      data1 <= #1 int_data113;
      data2 <= #1 int_data114;
      data3 <= #1 int_data115;
	end
    7'd114: begin
      data1 <= #1 int_data114;
      data2 <= #1 int_data115;
      data3 <= #1 int_data116;
	end
    7'd115: begin
      data1 <= #1 int_data115;
      data2 <= #1 int_data116;
      data3 <= #1 int_data117;
	end
    7'd116: begin
      data1 <= #1 int_data116;
      data2 <= #1 int_data117;
      data3 <= #1 int_data118;
	end
    7'd117: begin
      data1 <= #1 int_data117;
      data2 <= #1 int_data118;
      data3 <= #1 int_data119;
	end
    7'd118: begin
      data1 <= #1 int_data118;
      data2 <= #1 int_data119;
      data3 <= #1 int_data120;
	end
    7'd119: begin
      data1 <= #1 int_data119;
      data2 <= #1 int_data120;
      data3 <= #1 int_data121;
	end
    7'd120: begin
      data1 <= #1 int_data120;
      data2 <= #1 int_data121;
      data3 <= #1 int_data122;
	end
    7'd121: begin
      data1 <= #1 int_data121;
      data2 <= #1 int_data122;
      data3 <= #1 int_data123;
	end
    7'd122: begin
      data1 <= #1 int_data122;
      data2 <= #1 int_data123;
      data3 <= #1 int_data124;
	end
    7'd123: begin
      data1 <= #1 int_data123;
      data2 <= #1 int_data124;
      data3 <= #1 int_data125;
	end
    7'd124: begin
      data1 <= #1 int_data124;
      data2 <= #1 int_data125;
      data3 <= #1 int_data126;
	end
    7'd125: begin
      data1 <= #1 int_data125;
      data2 <= #1 int_data126;
      data3 <= #1 int_data127;
	end
    7'd126: begin
      data1 <= #1 int_data126;
      data2 <= #1 int_data127;
      data3 <= #1 int_data0;
	end
    7'd127: begin
      data1 <= #1 int_data127;
      data2 <= #1 int_data0;
      data3 <= #1 int_data1;
	end
    default: begin
      data1 <= #1 8'h00;
      data2 <= #1 8'h00;
      data3 <= #1 8'h00;
	end
  endcase
end

always @(posedge clk or posedge rst)
 if (rst)
   ea_int <= #1 1'b1;
  else ea_int <= #1 !ea;

`else


reg [7:0] buff [0:65535]; //64kb

assign ea = 1'b0;

initial
begin
  $readmemh("../../../bench/in/oc8051_rom.in", buff);
end

always @(posedge clk or posedge rst)
 if (rst)
   ea_int <= #1 1'b1;
  else ea_int <= #1 !ea;

always @(posedge clk)
begin
  data_o <= #1 {buff[addr+3], buff[addr+2], buff[addr+1], buff[addr]};
end


`endif


endmodule


`ifdef OC8051_XILINX_ROM

//rom0
module rom0 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=004760c0" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00475754" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=032c2000" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00300087" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0228b085" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=01002085" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=015378ed" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=024bd0c4" */;
endmodule

//rom1
module rom1 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=022c68a6" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0008e892" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=032feb64" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0010a020" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=015b2028" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00bca44c" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=02bc34c2" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=016700c3" */;
endmodule

//rom2
module rom2 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00701310" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=01a79000" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00a40cee" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=01371711" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=02340c6b" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=022c00c4" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=022c50c4" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00000aaa" */;
endmodule

//rom3
module rom3 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00f46b58" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=027c0c49" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0280bb9b" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00088848" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00807bbd" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00c30bf9" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=01b72fbd" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00343c40" */;
endmodule

//rom4
module rom4 (o,a);