oc8051_rom.v

verilog code,about oc8051

//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 internal program rom                                   ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////   internal program rom for 8051 core                         ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, [e-mail]                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: oc8051_rom.v,v $
// Revision 1.4  2003/07/01 20:47:39  simont
// add /* synopsys xx_case */ to case statments.
//
// Revision 1.3  2003/06/03 17:09:57  simont
// pipelined acces to axternal instruction interface added.
//
// Revision 1.2  2003/04/03 19:17:19  simont
// add `include "oc8051_defines.v"
//
// Revision 1.1  2003/04/02 11:16:22  simont
// initial inport
//
// Revision 1.4  2002/10/23 17:00:18  simont
// signal es_int=1'b0
//
// Revision 1.3  2002/09/30 17:34:01  simont
// prepared header
//
//
`include "oc8051_defines.v"

module oc8051_rom (rst, clk, addr, ea_int, data_o);

//parameter INT_ROM_WID= 15;

input rst, clk;
input [15:0] addr;
//input [22:0] addr;
output ea_int;
output [31:0] data_o;

reg [31:0] data_o;
wire ea;

reg ea_int;


`ifdef OC8051_XILINX_ROM

parameter INT_ROM_WID= 12;

reg [4:0] addr01;


wire [15:0] addr_rst;
wire [7:0] int_data0, int_data1, int_data2, int_data3, int_data4, int_data5, int_data6, int_data7, int_data8, int_data9, int_data10, int_data11, int_data12, int_data13, int_data14, int_data15, int_data16, int_data17, int_data18, int_data19, int_data20, int_data21, int_data22, int_data23, int_data24, int_data25, int_data26, int_data27, int_data28, int_data29, int_data30, int_data31, int_data32, int_data33, int_data34, int_data35, int_data36, int_data37, int_data38, int_data39, int_data40, int_data41, int_data42, int_data43, int_data44, int_data45, int_data46, int_data47, int_data48, int_data49, int_data50, int_data51, int_data52, int_data53, int_data54, int_data55, int_data56, int_data57, int_data58, int_data59, int_data60, int_data61, int_data62, int_data63, int_data64, int_data65, int_data66, int_data67, int_data68, int_data69, int_data70, int_data71, int_data72, int_data73, int_data74, int_data75, int_data76, int_data77, int_data78, int_data79, int_data80, int_data81, int_data82, int_data83, int_data84, int_data85, int_data86, int_data87, int_data88, int_data89, int_data90, int_data91, int_data92, int_data93, int_data94, int_data95, int_data96, int_data97, int_data98, int_data99, int_data100, int_data101, int_data102, int_data103, int_data104, int_data105, int_data106, int_data107, int_data108, int_data109, int_data110, int_data111, int_data112, int_data113, int_data114, int_data115, int_data116, int_data117, int_data118, int_data119, int_data120, int_data121, int_data122, int_data123, int_data124, int_data125, int_data126, int_data127;

assign ea = | addr[15:INT_ROM_WID];

assign addr_rst = rst ? 16'h0000 : addr;

  rom0 rom_0 (.a(addr01), .o(int_data0));
  rom1 rom_1 (.a(addr01), .o(int_data1));
  rom2 rom_2 (.a(addr_rst[11:7]), .o(int_data2));
  rom3 rom_3 (.a(addr_rst[11:7]), .o(int_data3));
  rom4 rom_4 (.a(addr_rst[11:7]), .o(int_data4));
  rom5 rom_5 (.a(addr_rst[11:7]), .o(int_data5));
  rom6 rom_6 (.a(addr_rst[11:7]), .o(int_data6));
  rom7 rom_7 (.a(addr_rst[11:7]), .o(int_data7));
  rom8 rom_8 (.a(addr_rst[11:7]), .o(int_data8));
  rom9 rom_9 (.a(addr_rst[11:7]), .o(int_data9));
  rom10 rom_10 (.a(addr_rst[11:7]), .o(int_data10));
  rom11 rom_11 (.a(addr_rst[11:7]), .o(int_data11));
  rom12 rom_12 (.a(addr_rst[11:7]), .o(int_data12));
  rom13 rom_13 (.a(addr_rst[11:7]), .o(int_data13));
  rom14 rom_14 (.a(addr_rst[11:7]), .o(int_data14));
  rom15 rom_15 (.a(addr_rst[11:7]), .o(int_data15));
  rom16 rom_16 (.a(addr_rst[11:7]), .o(int_data16));
  rom17 rom_17 (.a(addr_rst[11:7]), .o(int_data17));
  rom18 rom_18 (.a(addr_rst[11:7]), .o(int_data18));
  rom19 rom_19 (.a(addr_rst[11:7]), .o(int_data19));
  rom20 rom_20 (.a(addr_rst[11:7]), .o(int_data20));
  rom21 rom_21 (.a(addr_rst[11:7]), .o(int_data21));
  rom22 rom_22 (.a(addr_rst[11:7]), .o(int_data22));
  rom23 rom_23 (.a(addr_rst[11:7]), .o(int_data23));
  rom24 rom_24 (.a(addr_rst[11:7]), .o(int_data24));
  rom25 rom_25 (.a(addr_rst[11:7]), .o(int_data25));
  rom26 rom_26 (.a(addr_rst[11:7]), .o(int_data26));
  rom27 rom_27 (.a(addr_rst[11:7]), .o(int_data27));
  rom28 rom_28 (.a(addr_rst[11:7]), .o(int_data28));
  rom29 rom_29 (.a(addr_rst[11:7]), .o(int_data29));
  rom30 rom_30 (.a(addr_rst[11:7]), .o(int_data30));
  rom31 rom_31 (.a(addr_rst[11:7]), .o(int_data31));
  rom32 rom_32 (.a(addr_rst[11:7]), .o(int_data32));
  rom33 rom_33 (.a(addr_rst[11:7]), .o(int_data33));
  rom34 rom_34 (.a(addr_rst[11:7]), .o(int_data34));
  rom35 rom_35 (.a(addr_rst[11:7]), .o(int_data35));
  rom36 rom_36 (.a(addr_rst[11:7]), .o(int_data36));
  rom37 rom_37 (.a(addr_rst[11:7]), .o(int_data37));
  rom38 rom_38 (.a(addr_rst[11:7]), .o(int_data38));
  rom39 rom_39 (.a(addr_rst[11:7]), .o(int_data39));
  rom40 rom_40 (.a(addr_rst[11:7]), .o(int_data40));
  rom41 rom_41 (.a(addr_rst[11:7]), .o(int_data41));
  rom42 rom_42 (.a(addr_rst[11:7]), .o(int_data42));
  rom43 rom_43 (.a(addr_rst[11:7]), .o(int_data43));
  rom44 rom_44 (.a(addr_rst[11:7]), .o(int_data44));
  rom45 rom_45 (.a(addr_rst[11:7]), .o(int_data45));
  rom46 rom_46 (.a(addr_rst[11:7]), .o(int_data46));
  rom47 rom_47 (.a(addr_rst[11:7]), .o(int_data47));
  rom48 rom_48 (.a(addr_rst[11:7]), .o(int_data48));
  rom49 rom_49 (.a(addr_rst[11:7]), .o(int_data49));
  rom50 rom_50 (.a(addr_rst[11:7]), .o(int_data50));
  rom51 rom_51 (.a(addr_rst[11:7]), .o(int_data51));
  rom52 rom_52 (.a(addr_rst[11:7]), .o(int_data52));
  rom53 rom_53 (.a(addr_rst[11:7]), .o(int_data53));
  rom54 rom_54 (.a(addr_rst[11:7]), .o(int_data54));
  rom55 rom_55 (.a(addr_rst[11:7]), .o(int_data55));
  rom56 rom_56 (.a(addr_rst[11:7]), .o(int_data56));
  rom57 rom_57 (.a(addr_rst[11:7]), .o(int_data57));
  rom58 rom_58 (.a(addr_rst[11:7]), .o(int_data58));
  rom59 rom_59 (.a(addr_rst[11:7]), .o(int_data59));
  rom60 rom_60 (.a(addr_rst[11:7]), .o(int_data60));
  rom61 rom_61 (.a(addr_rst[11:7]), .o(int_data61));
  rom62 rom_62 (.a(addr_rst[11:7]), .o(int_data62));
  rom63 rom_63 (.a(addr_rst[11:7]), .o(int_data63));
  rom64 rom_64 (.a(addr_rst[11:7]), .o(int_data64));
  rom65 rom_65 (.a(addr_rst[11:7]), .o(int_data65));
  rom66 rom_66 (.a(addr_rst[11:7]), .o(int_data66));
  rom67 rom_67 (.a(addr_rst[11:7]), .o(int_data67));
  rom68 rom_68 (.a(addr_rst[11:7]), .o(int_data68));
  rom69 rom_69 (.a(addr_rst[11:7]), .o(int_data69));
  rom70 rom_70 (.a(addr_rst[11:7]), .o(int_data70));
  rom71 rom_71 (.a(addr_rst[11:7]), .o(int_data71));
  rom72 rom_72 (.a(addr_rst[11:7]), .o(int_data72));
  rom73 rom_73 (.a(addr_rst[11:7]), .o(int_data73));
  rom74 rom_74 (.a(addr_rst[11:7]), .o(int_data74));
  rom75 rom_75 (.a(addr_rst[11:7]), .o(int_data75));
  rom76 rom_76 (.a(addr_rst[11:7]), .o(int_data76));
  rom77 rom_77 (.a(addr_rst[11:7]), .o(int_data77));
  rom78 rom_78 (.a(addr_rst[11:7]), .o(int_data78));
  rom79 rom_79 (.a(addr_rst[11:7]), .o(int_data79));
  rom80 rom_80 (.a(addr_rst[11:7]), .o(int_data80));
  rom81 rom_81 (.a(addr_rst[11:7]), .o(int_data81));
  rom82 rom_82 (.a(addr_rst[11:7]), .o(int_data82));
  rom83 rom_83 (.a(addr_rst[11:7]), .o(int_data83));
  rom84 rom_84 (.a(addr_rst[11:7]), .o(int_data84));
  rom85 rom_85 (.a(addr_rst[11:7]), .o(int_data85));
  rom86 rom_86 (.a(addr_rst[11:7]), .o(int_data86));
  rom87 rom_87 (.a(addr_rst[11:7]), .o(int_data87));
  rom88 rom_88 (.a(addr_rst[11:7]), .o(int_data88));
  rom89 rom_89 (.a(addr_rst[11:7]), .o(int_data89));
  rom90 rom_90 (.a(addr_rst[11:7]), .o(int_data90));
  rom91 rom_91 (.a(addr_rst[11:7]), .o(int_data91));
  rom92 rom_92 (.a(addr_rst[11:7]), .o(int_data92));
  rom93 rom_93 (.a(addr_rst[11:7]), .o(int_data93));
  rom94 rom_94 (.a(addr_rst[11:7]), .o(int_data94));
  rom95 rom_95 (.a(addr_rst[11:7]), .o(int_data95));
  rom96 rom_96 (.a(addr_rst[11:7]), .o(int_data96));
  rom97 rom_97 (.a(addr_rst[11:7]), .o(int_data97));
  rom98 rom_98 (.a(addr_rst[11:7]), .o(int_data98));
  rom99 rom_99 (.a(addr_rst[11:7]), .o(int_data99));
  rom100 rom_100 (.a(addr_rst[11:7]), .o(int_data100));
  rom101 rom_101 (.a(addr_rst[11:7]), .o(int_data101));
  rom102 rom_102 (.a(addr_rst[11:7]), .o(int_data102));
  rom103 rom_103 (.a(addr_rst[11:7]), .o(int_data103));
  rom104 rom_104 (.a(addr_rst[11:7]), .o(int_data104));
  rom105 rom_105 (.a(addr_rst[11:7]), .o(int_data105));
  rom106 rom_106 (.a(addr_rst[11:7]), .o(int_data106));
  rom107 rom_107 (.a(addr_rst[11:7]), .o(int_data107));
  rom108 rom_108 (.a(addr_rst[11:7]), .o(int_data108));
  rom109 rom_109 (.a(addr_rst[11:7]), .o(int_data109));
  rom110 rom_110 (.a(addr_rst[11:7]), .o(int_data110));
  rom111 rom_111 (.a(addr_rst[11:7]), .o(int_data111));
  rom112 rom_112 (.a(addr_rst[11:7]), .o(int_data112));
  rom113 rom_113 (.a(addr_rst[11:7]), .o(int_data113));
  rom114 rom_114 (.a(addr_rst[11:7]), .o(int_data114));
  rom115 rom_115 (.a(addr_rst[11:7]), .o(int_data115));
  rom116 rom_116 (.a(addr_rst[11:7]), .o(int_data116));
  rom117 rom_117 (.a(addr_rst[11:7]), .o(int_data117));
  rom118 rom_118 (.a(addr_rst[11:7]), .o(int_data118));
  rom119 rom_119 (.a(addr_rst[11:7]), .o(int_data119));
  rom120 rom_120 (.a(addr_rst[11:7]), .o(int_data120));
  rom121 rom_121 (.a(addr_rst[11:7]), .o(int_data121));
  rom122 rom_122 (.a(addr_rst[11:7]), .o(int_data122));
  rom123 rom_123 (.a(addr_rst[11:7]), .o(int_data123));
  rom124 rom_124 (.a(addr_rst[11:7]), .o(int_data124));
  rom125 rom_125 (.a(addr_rst[11:7]), .o(int_data125));
  rom126 rom_126 (.a(addr_rst[11:7]), .o(int_data126));
  rom127 rom_127 (.a(addr_rst[11:7]), .o(int_data127));

always @(addr_rst)
begin
  if (addr_rst[1])
    addr01= addr_rst[11:7]+ 5'h1;
  else
    addr01= addr_rst[11:7];
end

//
// always read tree bits in row
always @(posedge clk)
begin
  case(addr[6:0]) /* synopsys parallel_case */
    7'd0: begin
      data1 <= #1 int_data0;
      data2 <= #1 int_data1;
      data3 <= #1 int_data2;
	end
    7'd1: begin
      data1 <= #1 int_data1;
      data2 <= #1 int_data2;
      data3 <= #1 int_data3;
	end
    7'd2: begin
      data1 <= #1 int_data2;
      data2 <= #1 int_data3;
      data3 <= #1 int_data4;
	end
    7'd3: begin
      data1 <= #1 int_data3;
      data2 <= #1 int_data4;
      data3 <= #1 int_data5;
	end
    7'd4: begin
      data1 <= #1 int_data4;
      data2 <= #1 int_data5;
      data3 <= #1 int_data6;
	end
    7'd5: begin
      data1 <= #1 int_data5;
      data2 <= #1 int_data6;
      data3 <= #1 int_data7;
	end
    7'd6: begin
      data1 <= #1 int_data6;
      data2 <= #1 int_data7;
      data3 <= #1 int_data8;
	end
    7'd7: begin
      data1 <= #1 int_data7;
      data2 <= #1 int_data8;
      data3 <= #1 int_data9;
	end
    7'd8: begin
      data1 <= #1 int_data8;
      data2 <= #1 int_data9;
      data3 <= #1 int_data10;
	end
    7'd9: begin
      data1 <= #1 int_data9;
      data2 <= #1 int_data10;
      data3 <= #1 int_data11;
	end
    7'd10: begin
      data1 <= #1 int_data10;
      data2 <= #1 int_data11;
      data3 <= #1 int_data12;
	end
    7'd11: begin
      data1 <= #1 int_data11;
      data2 <= #1 int_data12;
      data3 <= #1 int_data13;
	end
    7'd12: begin
      data1 <= #1 int_data12;
      data2 <= #1 int_data13;
      data3 <= #1 int_data14;
	end
    7'd13: begin
      data1 <= #1 int_data13;
      data2 <= #1 int_data14;
      data3 <= #1 int_data15;
	end
    7'd14: begin
      data1 <= #1 int_data14;
      data2 <= #1 int_data15;
      data3 <= #1 int_data16;
	end
    7'd15: begin
      data1 <= #1 int_data15;
      data2 <= #1 int_data16;
      data3 <= #1 int_data17;
	end
    7'd16: begin
      data1 <= #1 int_data16;
      data2 <= #1 int_data17;
      data3 <= #1 int_data18;
	end
    7'd17: begin
      data1 <= #1 int_data17;
      data2 <= #1 int_data18;