hdlc_transmit.vhd

HDLC的一些相关文档

--CDMA CDSU: HDLC transmit Module
--Designer: Tanshengbin
--Modify: 23.12.1999 by Tanshengbin
--All Rights Reserved, Dec, 1999

library	IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity HDLC_TRANSMIT is
port(Reset:		in			std_logic;

	 Data:		in			std_logic_vector(7 downto 0);
	 Add:		buffer		std_logic_vector(5 downto 0);
	 Rd:		buffer	 	std_logic;

	 Full:		in			std_logic;
	 Empty:		buffer 		std_logic;	
	
	 Hdlc_tclk:	in			std_logic;
	 Hdlc_txd:	buffer 		std_logic);
end entity;

architecture BEHAVIOR of HDLC_TRANSMIT is

	signal	Bit_counter			:	integer range 0 to 7;
	signal  Bit1_counter		:	integer range 0 to 7;
	signal  Trans_state			:	std_logic_vector(2 downto 0);
	signal	Shift_register		:	std_logic_vector(7 downto 0);
	signal  Total_byte_num		:	std_logic_vector(5 downto 0);
	signal	Crc_calculate_flag	:	std_logic;
--	signal	Crc_out				:   std_logic_vector(15 downto 0);

begin	
	--Empty
	process(Hdlc_tclk,Reset)
	begin
		if(Reset = '0')then
			Empty <= '1';
		elsif(Hdlc_tclk'event and Hdlc_tclk = '1')then
			if(Full = '1')then
				Empty <= '0';
			elsif(Trans_state = "101" or Trans_state = "010")then
				Empty <= '1';
			end if;
		end if;
	end process;

	--Trans_state
	process(Hdlc_tclk,Reset)
	begin
		if(Reset = '0')then
			Trans_state <= "000";
		elsif(Hdlc_tclk'event and Hdlc_tclk = '1')then
			case Trans_state is
				when "000" =>
					if(Empty = '0' and Bit_counter = 7)then
						Trans_state <= "001"; 
					end if;
				when "001" =>
					if(Bit_counter = 4)then
						if(Data >= "00110001" or Data < "00000110")then
							Trans_state <= "010";
						else
							Trans_state <= "011";
						end if;
					end if;
				when "010" =>
					Trans_state <= "000";
				when "011" =>
					if(Bit1_counter /= 5 and Bit_counter = 7 and Add = Total_byte_num + "000011")then
						Trans_state <= "100";
					end if;
				when "100" =>
					if(Bit_counter = 7)then
						Trans_state <= "101";
					end if;
				when "101" =>
					Trans_state <= "000";
				when others =>
					Trans_state <= "000";
			end case;
		end if;
	end process;

	--Add,Rd,Total_byte_num
	process(Hdlc_tclk,Reset)
	begin
		if(Reset = '0')then
			Add <= "000000";
			Total_byte_num <= "000000";
			Rd <= '0';
		elsif(Hdlc_tclk'event and Hdlc_tclk = '1')then
			if(Trans_state = "000")then
				Add <= "000000";
			elsif(Trans_state = "001")then
				if(Bit_counter = 0)then
					Rd <= '1';
				elsif(Bit_counter = 2)then
					Add <= "000001";
				elsif(Bit_counter = 4)then
					Rd <= '0';
					Total_byte_num <= Data(5 downto 0);
				end if;
			elsif(Trans_state = "011")then
				if(Bit1_counter/= 5 and Bit_counter = 2)then
					Add <= Add + "000001";
					Rd <= '1';
				else
					Rd <= '0';
				end if;
			end if;
		end if;
	end process;

	--Crc_calculate_flag
	process(Hdlc_tclk,Reset)
	begin
		if(Reset = '0')then
			Crc_calculate_flag <= '0';
		elsif(Hdlc_tclk'event and Hdlc_tclk = '1')then
			if(Trans_state /= "011")then
				Crc_calculate_flag <= '0';
			elsif(Bit_counter = 6 and Bit1_counter /= 5)then
				if(Add = Total_byte_num + "000001")then
					Crc_calculate_flag <= '0';	
				elsif(Add < Total_byte_num +"000001")then
					Crc_calculate_flag <= '1';	
				end if;		
			end if;
		end if;
	end process;


	--Shift_register
	process(Hdlc_tclk,Reset)
		variable crc_shift_var:	std_logic_vector(15 downto 0);
	begin
		if(Reset= '0')then
			Shift_register <="01111110";
			crc_shift_var := X"ffff";
			Hdlc_txd <= '0';
		elsif(Hdlc_tclk'event and Hdlc_tclk= '1')then
			if(Trans_state /= "011")then
				crc_shift_var := X"ffff";
                if(Bit_counter = 6)then
					Hdlc_txd <= Shift_register(0);
					Shift_register <= "01111110";
				else
					Hdlc_txd <= Shift_register(0);
					Shift_register(6 downto 0) <=Shift_register(7 downto 1);
				end if;
			elsif(Trans_state = "011")then
				if(Bit1_counter = 5)then
					Hdlc_txd <= '0';
				elsif(Bit_counter /= 6)then
					Hdlc_txd <= Shift_register(0);
					if(Crc_calculate_flag = '1')then
						if((crc_shift_var(0) xor Shift_register(0)) = '1')then
							crc_shift_var := crc_shift_var xor X"0810";
							crc_shift_var(14 downto 0) := crc_shift_var(15 downto 1);
							crc_shift_var(15) := '1';
						else
							crc_shift_var(14 downto 0) := crc_shift_var(15 downto 1);
							crc_shift_var(15) := '0';
						end if;
					end if;
					Shift_register(6 downto 0) <= Shift_register(7 downto 1);
				elsif(Add <= Total_byte_num)then
					Hdlc_txd <= Shift_register(0);
					if(Crc_calculate_flag = '1')then
						if((crc_shift_var(0) xor Shift_register(0)) = '1')then
							crc_shift_var := crc_shift_var xor X"0810";
							crc_shift_var(14 downto 0) := crc_shift_var(15 downto 1);
							crc_shift_var(15) := '1';
						else
							crc_shift_var(14 downto 0) := crc_shift_var(15 downto 1);
							crc_shift_var(15) := '0';
						end if;
					end if;
					Shift_register <= Data;
				elsif(Add = Total_byte_num + "000001")then
					Hdlc_txd <= Shift_register(0);
					if(Crc_calculate_flag = '1')then
						if((crc_shift_var(0) xor Shift_register(0)) = '1')then
							crc_shift_var := crc_shift_var xor X"0810";
							crc_shift_var(14 downto 0) := crc_shift_var(15 downto 1);
							crc_shift_var(15) := '1';
						else
							crc_shift_var(14 downto 0) := crc_shift_var(15 downto 1);
							crc_shift_var(15) := '0';
						end if;
					end if;
					Shift_register(7 downto 0) <= not(crc_shift_var(7 downto 0));
--					Shift_register(7 downto 0) <= Crc_out(7 downto 0);	
				elsif(Add = Total_byte_num +"000010")then
					Hdlc_txd <= Shift_register(0);
					Shift_register(7 downto 0) <= not(crc_shift_var(15 downto 8));	
--					Shift_register(7 downto 0) <= Crc_out(15 downto 8);	
				elsif(Add > Total_byte_num + "000010")then
					Hdlc_txd <= Shift_register(0);
					Shift_register <= "01111110";
				end if;
			end if;
		end if;
	end process; 


	--Bit_counter
	process(Hdlc_tclk,Reset)
	begin
		if(Reset = '0')then
			Bit_counter <= 7;
		elsif(Hdlc_tclk'event and Hdlc_tclk= '1')then
			if(Trans_state /= "011")then
				if(Hdlc_txd = '0' and Shift_register(0) = '0' and Bit_counter /= 0)then
					Bit_counter <= 0;
				else
					Bit_counter <= Bit_counter + 1;
				end if;
			else
				if(Bit1_counter /= 5)then	
					Bit_counter <= Bit_counter + 1;				
				end if;
			end if;
		end if;
	end process;
	
	--Bit1_counter
	process(Hdlc_tclk,Reset)
	begin
		if(Reset = '0')then
			Bit1_counter <= 0;
		elsif(Hdlc_tclk'event and Hdlc_tclk= '1')then
			if(Trans_state /= "011" )then
				Bit1_counter <= 0;
			elsif(Shift_register(0) = '0' or Bit1_counter = 5)then
				Bit1_counter <= 0;
			else
				Bit1_counter <= Bit1_counter + 1;
			end if;
		end if;
	end process;
 
end architecture;