📄 i2c_altera.tan.rpt
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; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; SYSCLK ; ; User Pin ; NONE ; 0.000 ns ; 0.000 ns ; NONE ; N/A ; N/A ; N/A ; ;
; altera_internal_jtag~TCKUTAP ; ; User Pin ; NONE ; 0.000 ns ; 0.000 ns ; NONE ; N/A ; N/A ; N/A ; ;
; PCLK ; ; User Pin ; NONE ; 0.000 ns ; 0.000 ns ; NONE ; N/A ; N/A ; N/A ; ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'SYSCLK' ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 178.19 MHz ( period = 5.612 ns ) ; i2c_cmd:inst|rom_addr[0] ; i2c_cmd:inst|rom_addr[5] ; SYSCLK ; SYSCLK ; None ; None ; 5.341 ns ;
; N/A ; 179.79 MHz ( period = 5.562 ns ) ; i2c_cmd:inst|rom_addr[0] ; i2c_cmd:inst|rom_addr[3] ; SYSCLK ; SYSCLK ; None ; None ; 5.291 ns ;
; N/A ; 187.02 MHz ( period = 5.347 ns ) ; i2c_cmd:inst|rom_addr[2] ; i2c_cmd:inst|rom_addr[5] ; SYSCLK ; SYSCLK ; None ; None ; 5.076 ns ;
; N/A ; 188.79 MHz ( period = 5.297 ns ) ; i2c_cmd:inst|rom_addr[2] ; i2c_cmd:inst|rom_addr[3] ; SYSCLK ; SYSCLK ; None ; None ; 5.026 ns ;
; N/A ; 189.07 MHz ( period = 5.289 ns ) ; i2c_cmd:inst|rom_addr[0] ; i2c_cmd:inst|rom_addr[6] ; SYSCLK ; SYSCLK ; None ; None ; 5.019 ns ;
; N/A ; 192.72 MHz ( period = 5.189 ns ) ; i2c_cmd:inst|rom_addr[1] ; i2c_cmd:inst|rom_addr[5] ; SYSCLK ; SYSCLK ; None ; None ; 4.918 ns ;
; N/A ; 194.59 MHz ( period = 5.139 ns ) ; i2c_cmd:inst|rom_addr[1] ; i2c_cmd:inst|rom_addr[3] ; SYSCLK ; SYSCLK ; None ; None ; 4.868 ns ;
; N/A ; 196.16 MHz ( period = 5.098 ns ) ; i2c_cmd:inst|rom_addr[4] ; i2c_cmd:inst|rom_addr[5] ; SYSCLK ; SYSCLK ; None ; None ; 4.827 ns ;
; N/A ; 196.73 MHz ( period = 5.083 ns ) ; i2c_cmd:inst|rom_addr[0] ; i2c_cmd:inst|rom_addr[2] ; SYSCLK ; SYSCLK ; None ; None ; 4.813 ns ;
; N/A ; 197.16 MHz ( period = 5.072 ns ) ; i2c_cmd:inst|rom_addr[3] ; i2c_cmd:inst|rom_addr[5] ; SYSCLK ; SYSCLK ; None ; None ; 4.802 ns ;
; N/A ; 197.63 MHz ( period = 5.060 ns ) ; i2c_cmd:inst|group_index ; i2c_cmd:inst|rom_addr[5] ; SYSCLK ; SYSCLK ; None ; None ; 4.789 ns ;
; N/A ; 198.10 MHz ( period = 5.048 ns ) ; i2c_cmd:inst|rom_addr[4] ; i2c_cmd:inst|rom_addr[3] ; SYSCLK ; SYSCLK ; None ; None ; 4.777 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; i2c_cmd:inst|rom_addr[1] ; SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_n1q:auto_generated|ram_block1a0~porta_address_reg1 ; SYSCLK ; SYSCLK ; None ; None ; 1.879 ns ;
; N/A ; 199.04 MHz ( period = 5.024 ns ) ; i2c_cmd:inst|rom_addr[2] ; i2c_cmd:inst|rom_addr[6] ; SYSCLK ; SYSCLK ; None ; None ; 4.754 ns ;
; N/A ; 199.12 MHz ( period = 5.022 ns ) ; i2c_cmd:inst|rom_addr[3] ; i2c_cmd:inst|rom_addr[3] ; SYSCLK ; SYSCLK ; None ; None ; 4.752 ns ;
; N/A ; 199.60 MHz ( period = 5.010 ns ) ; i2c_cmd:inst|group_index ; i2c_cmd:inst|rom_addr[3] ; SYSCLK ; SYSCLK ; None ; None ; 4.739 ns ;
; N/A ; 205.51 MHz ( period = 4.866 ns ) ; i2c_cmd:inst|rom_addr[0] ; i2c_cmd:inst|rom_addr[4] ; SYSCLK ; SYSCLK ; None ; None ; 4.596 ns ;
; N/A ; 205.51 MHz ( period = 4.866 ns ) ; i2c_cmd:inst|rom_addr[1] ; i2c_cmd:inst|rom_addr[6] ; SYSCLK ; SYSCLK ; None ; None ; 4.596 ns ;
; N/A ; 205.68 MHz ( period = 4.862 ns ) ; i2c_cmd:inst|rom_addr[6] ; i2c_cmd:inst|rom_addr[5] ; SYSCLK ; SYSCLK ; None ; None ; 4.591 ns ;
; N/A ; 207.04 MHz ( period = 4.830 ns ) ; i2c_cmd:inst|rom_addr[5] ; i2c_cmd:inst|rom_addr[5] ; SYSCLK ; SYSCLK ; None ; None ; 4.560 ns ;
; N/A ; 207.56 MHz ( period = 4.818 ns ) ; i2c_cmd:inst|rom_addr[2] ; i2c_cmd:inst|rom_addr[2] ; SYSCLK ; SYSCLK ; None ; None ; 4.548 ns ;
; N/A ; 207.81 MHz ( period = 4.812 ns ) ; i2c_cmd:inst|rom_addr[6] ; i2c_cmd:inst|rom_addr[3] ; SYSCLK ; SYSCLK ; None ; None ; 4.541 ns ;
; N/A ; 209.21 MHz ( period = 4.780 ns ) ; i2c_cmd:inst|rom_addr[5] ; i2c_cmd:inst|rom_addr[3] ; SYSCLK ; SYSCLK ; None ; None ; 4.510 ns ;
; N/A ; 209.42 MHz ( period = 4.775 ns ) ; i2c_cmd:inst|rom_addr[4] ; i2c_cmd:inst|rom_addr[6] ; SYSCLK ; SYSCLK ; None ; None ; 4.505 ns ;
; N/A ; 210.57 MHz ( period = 4.749 ns ) ; i2c_cmd:inst|rom_addr[3] ; i2c_cmd:inst|rom_addr[6] ; SYSCLK ; SYSCLK ; None ; None ; 4.480 ns ;
; N/A ; 211.10 MHz ( period = 4.737 ns ) ; i2c_cmd:inst|group_index ; i2c_cmd:inst|rom_addr[6] ; SYSCLK ; SYSCLK ; None ; None ; 4.467 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; i2c_cmd:inst|rom_addr[2] ; SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_n1q:auto_generated|ram_block1a0~porta_address_reg2 ; SYSCLK ; SYSCLK ; None ; None ; 1.549 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; i2c_cmd:inst|rom_addr[4] ; SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_n1q:auto_generated|ram_block1a0~porta_address_reg4 ; SYSCLK ; SYSCLK ; None ; None ; 1.545 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; i2c_cmd:inst|rom_addr[5] ; SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_n1q:auto_generated|ram_block1a0~porta_address_reg5 ; SYSCLK ; SYSCLK ; None ; None ; 1.544 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; i2c_cmd:inst|rom_addr[0] ; SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_n1q:auto_generated|ram_block1a0~porta_address_reg0 ; SYSCLK ; SYSCLK ; None ; None ; 1.534 ns ;
; N/A ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; i2c_cmd:inst|rom_addr[6] ; SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_n1q:auto_generated|ram_block1a0~porta_address_reg6 ; SYSCLK ; SYSCLK ; None ; None ; 1.525 ns ;
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