i2c_altera.tan.rpt

来自「AV视频信号输入后」· RPT 代码 · 共 216 行 · 第 1/5 页

; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+---------------------------------------------+------------------------------------------+---------------+------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack                                    ; Required Time ; Actual Time                                    ; From                                                                                                                                                                              ; To                                                                                                                                                                  ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+------------------------------------------+---------------+------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A                                      ; None          ; 6.198 ns                                       ; VD_VS                                                                                                                                                                             ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[8]                                                                                                                ;                              ; PCLK                         ; 0            ;
; Worst-case tco                              ; N/A                                      ; None          ; 12.427 ns                                      ; Led_run:inst21|led[3]                                                                                                                                                             ; LEDG[3]                                                                                                                                                             ; SYSCLK                       ;                              ; 0            ;
; Worst-case tpd                              ; N/A                                      ; None          ; 2.901 ns                                       ; altera_internal_jtag~TDO                                                                                                                                                          ; altera_reserved_tdo                                                                                                                                                 ;                              ;                              ; 0            ;
; Worst-case th                               ; N/A                                      ; None          ; 1.659 ns                                       ; altera_internal_jtag~TMSUTAP                                                                                                                                                      ; sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[14]                                                                                            ;                              ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A                                      ; None          ; 132.56 MHz ( period = 7.544 ns )               ; sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3]                                                                                                                                ; sld_hub:sld_hub_inst|hub_tdo                                                                                                                                        ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'PCLK'                         ; N/A                                      ; None          ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_95a:auto_generated|safe_q[0] ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_nm92:auto_generated|altsyncram_td91:altsyncram1|ram_block2a7~portb_we_reg ; PCLK                         ; PCLK                         ; 0            ;
; Clock Setup: 'SYSCLK'                       ; N/A                                      ; None          ; 178.19 MHz ( period = 5.612 ns )               ; i2c_cmd:inst|rom_addr[0]                                                                                                                                                          ; i2c_cmd:inst|rom_addr[5]                                                                                                                                            ; SYSCLK                       ; SYSCLK                       ; 0            ;
; Clock Hold: 'SYSCLK'                        ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_n1q:auto_generated|q_a[7]                                                                                                ; i2c_cmd:inst|i2c_data_t[7]                                                                                                                                          ; SYSCLK                       ; SYSCLK                       ; 12           ;
; Total number of failed paths                ;                                          ;               ;                                                ;                                                                                                                                                                                   ;                                                                                                                                                                     ;                              ;                              ; 12           ;
+---------------------------------------------+------------------------------------------+---------------+------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C20F484C8       ;      ;    ;             ;
; Timing Models                                         ; Preliminary        ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; On                 ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                          ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+