snake.tan.rpt

利用VHDL语言编写的一个蛇形的程序

; Slack ; Required tco ; Actual tco ; From         ; To      ; From Clock ;
+-------+--------------+------------+--------------+---------+------------+
; N/A   ; None         ; 12.563 ns  ; SCAN[4]~reg0 ; SCAN[4] ; CLK        ;
; N/A   ; None         ; 12.532 ns  ; SCAN[1]~reg0 ; SCAN[1] ; CLK        ;
; N/A   ; None         ; 12.522 ns  ; SCAN[5]~reg0 ; SCAN[5] ; CLK        ;
; N/A   ; None         ; 12.510 ns  ; SCAN[3]~reg0 ; SCAN[3] ; CLK        ;
; N/A   ; None         ; 12.502 ns  ; SCAN[2]~reg0 ; SCAN[2] ; CLK        ;
; N/A   ; None         ; 12.327 ns  ; SEG7[4]~reg0 ; SEG7[4] ; CLK        ;
; N/A   ; None         ; 12.294 ns  ; SEG7[7]~reg0 ; SEG7[7] ; CLK        ;
; N/A   ; None         ; 12.276 ns  ; SEG7[6]~reg0 ; SEG7[6] ; CLK        ;
; N/A   ; None         ; 12.246 ns  ; SEG7[5]~reg0 ; SEG7[5] ; CLK        ;
; N/A   ; None         ; 12.232 ns  ; SEG7[8]~reg0 ; SEG7[8] ; CLK        ;
; N/A   ; None         ; 11.970 ns  ; SEG7[1]~reg0 ; SEG7[1] ; CLK        ;
; N/A   ; None         ; 11.966 ns  ; SEG7[3]~reg0 ; SEG7[3] ; CLK        ;
; N/A   ; None         ; 11.961 ns  ; SEG7[2]~reg0 ; SEG7[2] ; CLK        ;
+-------+--------------+------------+--------------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Tue Jun 06 11:20:40 2006
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off Snake -c Snake --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node CLK is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock clk_2HZ as buffer
    Info: Detected ripple clock count[8] as buffer
Info: Clock CLK has Internal fmax of 211.82 MHz between source register count[22] and destination register clk_2HZ (period= 4.721 ns)
    Info: + Longest register to register delay is 4.431 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y13_N7; Fanout = 4; REG Node = 'count[22]'
        Info: 2: + IC(1.261 ns) + CELL(0.590 ns) = 1.851 ns; Loc. = LC_X6_Y14_N2; Fanout = 1; COMB Node = 'reduce_nor~211'
        Info: 3: + IC(0.450 ns) + CELL(0.292 ns) = 2.593 ns; Loc. = LC_X6_Y14_N3; Fanout = 9; COMB Node = 'reduce_nor~215'
        Info: 4: + IC(1.529 ns) + CELL(0.309 ns) = 4.431 ns; Loc. = LC_X8_Y10_N0; Fanout = 31; REG Node = 'clk_2HZ'
        Info: Total cell delay = 1.191 ns ( 26.88 % )
        Info: Total interconnect delay = 3.240 ns ( 73.12 % )
    Info: - Smallest clock skew is -0.029 ns
        Info: + Shortest clock path from clock CLK to destination register is 2.902 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 25; CLK Node = 'CLK'
            Info: 2: + IC(0.722 ns) + CELL(0.711 ns) = 2.902 ns; Loc. = LC_X8_Y10_N0; Fanout = 31; REG Node = 'clk_2HZ'
            Info: Total cell delay = 2.180 ns ( 75.12 % )
            Info: Total interconnect delay = 0.722 ns ( 24.88 % )
        Info: - Longest clock path from clock CLK to source register is 2.931 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 25; CLK Node = 'CLK'
            Info: 2: + IC(0.751 ns) + CELL(0.711 ns) = 2.931 ns; Loc. = LC_X7_Y13_N7; Fanout = 4; REG Node = 'count[22]'
            Info: Total cell delay = 2.180 ns ( 74.38 % )
            Info: Total interconnect delay = 0.751 ns ( 25.62 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register snak[27] (data pin = RST, clock pin = CLK) is 4.181 ns
    Info: + Longest pin to register delay is 11.173 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_1; Fanout = 28; PIN Node = 'RST'
        Info: 2: + IC(7.408 ns) + CELL(0.590 ns) = 9.467 ns; Loc. = LC_X5_Y7_N9; Fanout = 7; COMB Node = 'snak~525'
        Info: 3: + IC(1.228 ns) + CELL(0.478 ns) = 11.173 ns; Loc. = LC_X6_Y8_N6; Fanout = 1; REG Node = 'snak[27]'
        Info: Total cell delay = 2.537 ns ( 22.71 % )
        Info: Total interconnect delay = 8.636 ns ( 77.29 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock CLK to destination register is 7.029 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 25; CLK Node = 'CLK'
        Info: 2: + IC(0.722 ns) + CELL(0.935 ns) = 3.126 ns; Loc. = LC_X8_Y10_N0; Fanout = 31; REG Node = 'clk_2HZ'
        Info: 3: + IC(3.192 ns) + CELL(0.711 ns) = 7.029 ns; Loc. = LC_X6_Y8_N6; Fanout = 1; REG Node = 'snak[27]'
        Info: Total cell delay = 3.115 ns ( 44.32 % )
        Info: Total interconnect delay = 3.914 ns ( 55.68 % )
Info: tco from clock CLK to destination pin SCAN[4] through register SCAN[4]~reg0 is 12.563 ns
    Info: + Longest clock path from clock CLK to source register is 7.803 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 25; CLK Node = 'CLK'
        Info: 2: + IC(0.751 ns) + CELL(0.935 ns) = 3.155 ns; Loc. = LC_X6_Y14_N2; Fanout = 20; REG Node = 'count[8]'
        Info: 3: + IC(3.937 ns) + CELL(0.711 ns) = 7.803 ns; Loc. = LC_X7_Y5_N5; Fanout = 1; REG Node = 'SCAN[4]~reg0'
        Info: Total cell delay = 3.115 ns ( 39.92 % )
        Info: Total interconnect delay = 4.688 ns ( 60.08 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 4.536 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y5_N5; Fanout = 1; REG Node = 'SCAN[4]~reg0'
        Info: 2: + IC(2.428 ns) + CELL(2.108 ns) = 4.536 ns; Loc. = PIN_86; Fanout = 0; PIN Node = 'SCAN[4]'
        Info: Total cell delay = 2.108 ns ( 46.47 % )
        Info: Total interconnect delay = 2.428 ns ( 53.53 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Tue Jun 06 11:20:40 2006
    Info: Elapsed time: 00:00:00