snake.map.rpt

利用VHDL语言编写的一个蛇形的程序

; Number of synthesis-generated cells                    ; 120   ;
; Number of WYSIWYG LUTs                                 ; 30    ;
; Number of synthesis-generated LUTs                     ; 102   ;
; Number of WYSIWYG registers                            ; 1     ;
; Number of synthesis-generated registers                ; 71    ;
; Number of cells with combinational logic only          ; 78    ;
; Number of cells with registers only                    ; 18    ;
; Number of cells with combinational logic and registers ; 54    ;
+--------------------------------------------------------+-------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear  ; 1     ;
; Number of registers using Synchronous Load   ; 1     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 4     ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------+
; Hierarchy ;
+-----------+
Snake


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                       ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |Snake                     ; 150 (150)   ; 72           ; 0           ; 18   ; 0            ; 78 (78)      ; 18 (18)           ; 54 (54)          ; 29 (29)         ; |Snake              ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in I:/共享/310exp_BY_Dong/02 snake/Snake.map.eqn.


+----------------------------------------+
; Analysis & Synthesis Source Files Read ;
+-----------+----------------------------+
; File Name ; Used in Netlist            ;
+-----------+----------------------------+
; Snake.v   ; yes                        ;
+-----------+----------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Logic cells                       ; 150     ;
; Total combinational functions     ; 132     ;
; Total 4-input functions           ; 68      ;
; Total 3-input functions           ; 20      ;
; Total 2-input functions           ; 15      ;
; Total 1-input functions           ; 29      ;
; Total 0-input functions           ; 0       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 72      ;
; Total logic cells in carry chains ; 29      ;
; I/O pins                          ; 18      ;
; Maximum fan-out node              ; clk_2HZ ;
; Maximum fan-out                   ; 31      ;
; Total fan-out                     ; 528     ;
; Average fan-out                   ; 3.14    ;
+-----------------------------------+---------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Tue Jun 06 11:20:23 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off Snake -c Snake
Info: Found 1 design units, including 1 entities, in source file Snake.v
    Info: Found entity 1: Snake
Warning: Verilog HDL expression warning at Snake.v(21): truncated operand with size 25 to match size of smaller operand (24)
Warning: Verilog HDL expression warning at Snake.v(40): truncated operand with size 3 to match size of smaller operand (2)
Warning: Verilog HDL expression warning at Snake.v(43): truncated operand with size 6 to match size of smaller operand (5)
Warning: Verilog HDL expression warning at Snake.v(81): truncated operand with size 3 to match size of smaller operand (2)
Warning: Verilog HDL expression warning at Snake.v(84): truncated operand with size 6 to match size of smaller operand (5)
Warning: Verilog HDL expression warning at Snake.v(122): truncated operand with size 4 to match size of smaller operand (3)
Warning: Reduced register snak[30] with stuck data_in port to stuck value GND
Warning: Reduced register snak[29] with stuck data_in port to stuck value GND
Warning: Reduced register snak[24] with stuck data_in port to stuck value GND
Warning: Reduced register snak[22] with stuck data_in port to stuck value GND
Warning: Reduced register snak[21] with stuck data_in port to stuck value GND
Warning: Reduced register snak[19] with stuck data_in port to stuck value GND
Warning: Reduced register snak[18] with stuck data_in port to stuck value GND
Warning: Reduced register snak[16] with stuck data_in port to stuck value GND
Warning: Reduced register snak[14] with stuck data_in port to stuck value GND
Warning: Reduced register snak[13] with stuck data_in port to stuck value GND
Warning: Reduced register snak[11] with stuck data_in port to stuck value GND
Warning: Reduced register snak[10] with stuck data_in port to stuck value GND
Warning: Reduced register snak[8] with stuck data_in port to stuck value GND
Warning: Reduced register snak[3] with stuck data_in port to stuck value GND
Warning: Reduced register snak[2] with stuck data_in port to stuck value GND
Warning: Reduced register snak[0] with stuck data_in port to stuck value GND
Warning: Reduced register SCAN[6]~reg0 with stuck data_in port to stuck value GND
Warning: Reduced register SCAN[7]~reg0 with stuck data_in port to stuck value GND
Warning: Reduced register SCAN[8]~reg0 with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register q[4] merged to single register q[1]
Warning: Output pins are stuck at VCC or GND
    Warning: Pin SCAN[6] stuck at GND
    Warning: Pin SCAN[7] stuck at GND
    Warning: Pin SCAN[8] stuck at GND
Info: Implemented 168 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 16 output pins
    Info: Implemented 150 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 29 warnings
    Info: Processing ended: Tue Jun 06 11:20:26 2006
    Info: Elapsed time: 00:00:02