speaker.vhd

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity speaker is
  port(clk:in std_logic;
       tone:in std_logic_vector(10 downto 0);
       spks:out std_logic);
  end;

architecture one of speaker is
signal preclk:std_logic;
signal fullspks:std_logic;
signal tone1:integer range 0 to 16#7ff#;
signal count4:integer range 0 to 15;
begin
  tone1<=conv_integer(tone);
  divideclk:process(clk)
begin
  if clk'event and clk='1' then
    if count4 = 4 then
        count4 <= 0;
        preclk<='1';  
     else 
        count4<=count4+1;
        preclk<='0'; 
   end if;
  end if;
end process;
genspks:process(preclk,tone1)
variable count11:integer range 0 to 16#7ff#;
begin
  if preclk'event and preclk='1' then
  if count11=16#7ff# then
    count11:=tone1;
    fullspks<='1';
    else count11:=count11+1;
    fullspks<='0';
    end if;
    end if;
end process;
delayspks:process(fullspks)
variable count2:std_logic;
begin
if fullspks'event and fullspks='1' then
count2:=not count2;
if count2='1' then
  spks<='1';
else
  spks<='0';
end if;
end if;
end process;
end one;