f50k.hier_info

VHDL产生时钟50分频程序

|f50k
clk => clk2.CLK
clk => y2[0].CLK
clk => y2[1].CLK
clk => y2[2].CLK
clk => y2[3].CLK
clk => y2[4].CLK
clk => clk1.CLK
clk => y1[0].CLK
clk => y1[1].CLK
clk => y1[2].CLK
clk => y1[3].CLK
clk => y1[4].CLK
clk => y1[5].CLK
clk => y1[6].CLK
clk => y1[7].CLK
clk => y1[8].CLK
clk => y1[9].CLK
clk => y1[10].CLK
clk => y1[11].CLK
clk => y1[12].CLK
clk => y1[13].CLK
reset => y1~14.OUTPUTSELECT
reset => y1~15.OUTPUTSELECT
reset => y1~16.OUTPUTSELECT
reset => y1~17.OUTPUTSELECT
reset => y1~18.OUTPUTSELECT
reset => y1~19.OUTPUTSELECT
reset => y1~20.OUTPUTSELECT
reset => y1~21.OUTPUTSELECT
reset => y1~22.OUTPUTSELECT
reset => y1~23.OUTPUTSELECT
reset => y1~24.OUTPUTSELECT
reset => y1~25.OUTPUTSELECT
reset => y1~26.OUTPUTSELECT
reset => y1~27.OUTPUTSELECT
reset => clk1~1.OUTPUTSELECT
reset => y2~5.OUTPUTSELECT
reset => y2~6.OUTPUTSELECT
reset => y2~7.OUTPUTSELECT
reset => y2~8.OUTPUTSELECT
reset => y2~9.OUTPUTSELECT
reset => clk2~1.OUTPUTSELECT
reset => temp[8]~50.OUTPUTSELECT
reset => temp[7]~49.OUTPUTSELECT
reset => temp[6]~48.OUTPUTSELECT
reset => temp[5]~47.OUTPUTSELECT
reset => temp[4]~46.OUTPUTSELECT
reset => temp[3]~45.OUTPUTSELECT
reset => temp[2]~44.OUTPUTSELECT
reset => temp[1]~43.OUTPUTSELECT
reset => temp[0]~42.OUTPUTSELECT
reset => q.ALOAD
reset => c1.ACLR
reset => c2.ACLR
reset => c3.PRESET
reset => b.ENA
qout[0] <= qout[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
qout[1] <= qout[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
qout[2] <= qout[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
qout[3] <= qout[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
qout[4] <= qout[4]$latch.DB_MAX_OUTPUT_PORT_TYPE
qout[5] <= qout[5]$latch.DB_MAX_OUTPUT_PORT_TYPE
qout[6] <= qout[6]$latch.DB_MAX_OUTPUT_PORT_TYPE
qout[7] <= qout[7]$latch.DB_MAX_OUTPUT_PORT_TYPE